Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 3 | #include <console/console.h> |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 5 | #include <device/smbus_host.h> |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/common/gpio.h> |
| 7 | #include <southbridge/intel/common/pmbase.h> |
Elyes Haouas | f360006 | 2022-10-03 11:01:31 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/common/rcba.h> |
| 9 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 10 | #include "chip.h" |
Elyes Haouas | f360006 | 2022-10-03 11:01:31 +0200 | [diff] [blame] | 11 | #include "i82801gx.h" |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 12 | |
| 13 | void i82801gx_lpc_setup(void) |
| 14 | { |
| 15 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
| 16 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 17 | const struct southbridge_intel_i82801gx_config *config; |
| 18 | |
| 19 | /* Configure serial IRQs.*/ |
| 20 | pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0); |
| 21 | /* |
| 22 | * Enable some common LPC IO ranges: |
| 23 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 24 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 25 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 26 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 27 | * - 0x2f8-0x2ff COMB |
| 28 | * - 0x3f8-0x3ff COMA |
| 29 | * - 0x208-0x20f GAMEH |
| 30 | * - 0x200-0x207 GAMEL |
| 31 | */ |
| 32 | pci_write_config16(d31f0, LPC_IO_DEC, 0x0010); |
| 33 | pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN |
| 34 | | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN |
| 35 | | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN |
| 36 | | COMB_LPC_EN | COMA_LPC_EN); |
| 37 | |
| 38 | /* Set up generic decode ranges */ |
| 39 | if (!dev || !dev->chip_info) |
| 40 | return; |
| 41 | config = dev->chip_info; |
| 42 | |
| 43 | pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec); |
| 44 | pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec); |
| 45 | pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); |
| 46 | pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); |
| 47 | } |
Arthur Heymans | b236352 | 2019-11-11 18:40:50 +0100 | [diff] [blame] | 48 | |
| 49 | void i82801gx_setup_bars(void) |
| 50 | { |
| 51 | const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 52 | pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); |
Arthur Heymans | b236352 | 2019-11-11 18:40:50 +0100 | [diff] [blame] | 53 | pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); |
| 54 | pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); |
| 55 | |
| 56 | pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 57 | pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); |
| 58 | } |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 59 | |
Kyösti Mälkki | f38f30a | 2022-11-25 06:22:10 +0200 | [diff] [blame] | 60 | #define TCO_BASE 0x60 |
| 61 | |
Kyösti Mälkki | 11cac78 | 2022-04-07 07:16:48 +0300 | [diff] [blame] | 62 | #if ENV_RAMINIT |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 63 | void i82801gx_early_init(void) |
| 64 | { |
Kyösti Mälkki | 7adc370 | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 65 | enable_smbus(); |
| 66 | |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 67 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 68 | i82801gx_setup_bars(); |
| 69 | |
| 70 | setup_pch_gpios(&mainboard_gpio_map); |
| 71 | printk(BIOS_DEBUG, " done.\n"); |
| 72 | |
| 73 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 74 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Kyösti Mälkki | f38f30a | 2022-11-25 06:22:10 +0200 | [diff] [blame] | 75 | write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ |
| 76 | write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ |
| 77 | write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 78 | printk(BIOS_DEBUG, " done.\n"); |
| 79 | |
| 80 | /* program secondary mlt XXX byte? */ |
| 81 | pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); |
| 82 | |
| 83 | /* reset rtc power status */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame] | 84 | pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 85 | |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 86 | /* USB transient disconnect */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame] | 87 | pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 88 | |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame] | 89 | pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17)); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 90 | |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame] | 91 | pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27)); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 92 | |
| 93 | /* Enable IOAPIC */ |
| 94 | RCBA8(OIC) = 0x03; |
| 95 | RCBA8(OIC); |
| 96 | |
Arthur Heymans | a1928cf | 2019-11-13 10:51:59 +0100 | [diff] [blame] | 97 | /* A lot of CIR bits relate DMI setup which is likely not correctly |
| 98 | done for x4x. The issue is also present on ICH10. */ |
| 99 | if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) |
| 100 | ich7_setup_cir(); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 101 | } |
| 102 | #endif |