Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 4 | #include <arch/hpet.h> |
Patrick Rudolph | 57ddd68 | 2023-02-28 09:17:40 +0100 | [diff] [blame] | 5 | #include <arch/ioapic.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 6 | #include <assert.h> |
| 7 | #include <cbmem.h> |
Naresh Solanki | 559f9ed | 2023-01-20 19:38:07 +0100 | [diff] [blame] | 8 | #include <cpu/x86/lapic.h> |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 9 | #include <commonlib/sort.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 10 | #include <device/mmio.h> |
| 11 | #include <device/pci.h> |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 12 | #include <device/pciexp.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 13 | #include <soc/acpi.h> |
Rocky Phagura | d4db36e | 2021-04-03 08:49:32 -0700 | [diff] [blame] | 14 | #include <soc/hest.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 15 | #include <soc/iomap.h> |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 16 | #include <soc/numa.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/soc_util.h> |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 19 | #include <soc/util.h> |
Arthur Heymans | 695dd29 | 2020-11-12 21:05:09 +0100 | [diff] [blame] | 20 | #include <intelblocks/p2sb.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 21 | |
| 22 | #include "chip.h" |
| 23 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 24 | /* NUMA related ACPI table generation. SRAT, SLIT, etc */ |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 25 | |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 26 | /* Increase if necessary. Currently all x86 CPUs only have 2 SMP threads */ |
| 27 | #define MAX_THREAD 2 |
| 28 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 29 | unsigned long acpi_create_srat_lapics(unsigned long current) |
| 30 | { |
| 31 | struct device *cpu; |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 32 | unsigned int num_cpus = 0; |
| 33 | int apic_ids[CONFIG_MAX_CPUS] = {}; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 34 | |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 35 | unsigned int sort_start = 0; |
| 36 | for (unsigned int thread_id = 0; thread_id < MAX_THREAD; thread_id++) { |
| 37 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 38 | if (!is_enabled_cpu(cpu)) |
| 39 | continue; |
| 40 | if (num_cpus >= ARRAY_SIZE(apic_ids)) |
| 41 | break; |
| 42 | if (cpu->path.apic.thread_id != thread_id) |
| 43 | continue; |
| 44 | apic_ids[num_cpus++] = cpu->path.apic.apic_id; |
| 45 | } |
| 46 | bubblesort(&apic_ids[sort_start], num_cpus - sort_start, NUM_ASCENDING); |
| 47 | sort_start = num_cpus; |
| 48 | } |
| 49 | |
| 50 | for (unsigned int i = 0; i < num_cpus; i++) { |
| 51 | /* Match the sorted apic_ids to a struct device */ |
| 52 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 53 | if (!is_enabled_cpu(cpu)) |
| 54 | continue; |
| 55 | if (cpu->path.apic.apic_id == apic_ids[i]) |
| 56 | break; |
| 57 | } |
| 58 | if (!cpu) |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 59 | continue; |
Naresh Solanki | 559f9ed | 2023-01-20 19:38:07 +0100 | [diff] [blame] | 60 | |
| 61 | if (is_x2apic_mode()) { |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 62 | printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%04x, node_id=%02x, apic_id=%08x\n", |
| 63 | i, cpu->path.apic.node_id, cpu->path.apic.apic_id); |
Naresh Solanki | 559f9ed | 2023-01-20 19:38:07 +0100 | [diff] [blame] | 64 | |
| 65 | current += acpi_create_srat_x2apic((acpi_srat_x2apic_t *)current, |
| 66 | cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 67 | } else { |
| 68 | printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", |
Arthur Heymans | 36e6f9b | 2022-10-27 15:11:05 +0200 | [diff] [blame] | 69 | i, cpu->path.apic.node_id, cpu->path.apic.apic_id); |
Naresh Solanki | 559f9ed | 2023-01-20 19:38:07 +0100 | [diff] [blame] | 70 | |
| 71 | current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, |
| 72 | cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 73 | } |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 74 | } |
| 75 | return current; |
| 76 | } |
| 77 | |
| 78 | static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) |
| 79 | { |
| 80 | const struct SystemMemoryMapHob *memory_map; |
| 81 | unsigned int mmap_index; |
| 82 | |
| 83 | memory_map = get_system_memory_map(); |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 84 | assert(memory_map); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); |
| 86 | |
| 87 | mmap_index = 0; |
| 88 | for (int e = 0; e < memory_map->numberEntries; ++e) { |
| 89 | const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; |
| 90 | uint64_t addr = |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 91 | (uint64_t)((uint64_t)mem_element->BaseAddress << |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 92 | MEM_ADDR_64MB_SHIFT_BITS); |
| 93 | uint64_t size = |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 94 | (uint64_t)((uint64_t)mem_element->ElementSize << |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 95 | MEM_ADDR_64MB_SHIFT_BITS); |
| 96 | |
| 97 | printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 98 | "ElementSize: 0x%x, type: %d, reserved: %d\n", |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 99 | e, addr, mem_element->BaseAddress, size, |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 100 | mem_element->ElementSize, mem_element->Type, |
| 101 | (mem_element->Type & MEM_TYPE_RESERVED)); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 102 | |
| 103 | assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); |
| 104 | |
| 105 | /* skip reserved memory region */ |
| 106 | if (mem_element->Type & MEM_TYPE_RESERVED) |
| 107 | continue; |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 108 | #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) |
| 109 | /* Skip all non processor attached memory regions */ |
| 110 | /* In other words, skip all the types >= MemTypeCxlAccVolatileMem */ |
| 111 | if (mem_element->Type >= MemTypeCxlAccVolatileMem) |
| 112 | continue; |
| 113 | #endif |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 114 | |
| 115 | /* skip if this address is already added */ |
| 116 | bool skip = false; |
| 117 | for (int idx = 0; idx < mmap_index; ++idx) { |
| 118 | uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + |
| 119 | srat_mem[idx].base_address_low; |
| 120 | if (addr == base_addr) { |
| 121 | skip = true; |
| 122 | break; |
| 123 | } |
| 124 | } |
| 125 | if (skip) |
| 126 | continue; |
| 127 | |
| 128 | srat_mem[mmap_index].type = 1; /* Memory affinity structure */ |
| 129 | srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 130 | srat_mem[mmap_index].base_address_low = (uint32_t)(addr & 0xffffffff); |
| 131 | srat_mem[mmap_index].base_address_high = (uint32_t)(addr >> 32); |
| 132 | srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff); |
| 133 | srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 134 | srat_mem[mmap_index].proximity_domain = mem_element->SocketId; |
| 135 | srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; |
| 136 | if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) |
| 137 | srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; |
| 138 | ++mmap_index; |
| 139 | } |
| 140 | |
| 141 | return mmap_index; |
| 142 | } |
| 143 | |
| 144 | static unsigned long acpi_fill_srat(unsigned long current) |
| 145 | { |
| 146 | acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; |
| 147 | unsigned int mem_count; |
| 148 | |
| 149 | /* create all subtables for processors */ |
| 150 | current = acpi_create_srat_lapics(current); |
| 151 | |
| 152 | mem_count = get_srat_memory_entries(srat_mem); |
| 153 | for (int i = 0; i < mem_count; ++i) { |
| 154 | printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " |
| 155 | "length: 0x%x%x, proximity_domain: %d, flags: %x\n", |
| 156 | i, srat_mem[i].length, |
| 157 | srat_mem[i].base_address_high, srat_mem[i].base_address_low, |
| 158 | srat_mem[i].length_high, srat_mem[i].length_low, |
| 159 | srat_mem[i].proximity_domain, srat_mem[i].flags); |
| 160 | memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); |
| 161 | current += srat_mem[i].length; |
| 162 | } |
| 163 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 164 | if (CONFIG(SOC_INTEL_HAS_CXL)) |
| 165 | current = cxl_fill_srat(current); |
| 166 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 167 | return current; |
| 168 | } |
| 169 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 170 | #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) |
| 171 | /* |
| 172 | Because pds.num_pds comes from spr/numa.c function fill_pds(). |
| 173 | pds.num_pds = soc_get_num_cpus() + get_cxl_node_count(). |
| 174 | */ |
| 175 | /* SPR-SP platform has Generic Initiator domain in addition to processor domain */ |
| 176 | static unsigned long acpi_fill_slit(unsigned long current) |
| 177 | { |
| 178 | uint8_t *p = (uint8_t *)current; |
| 179 | /* According to table 5.60 of ACPI 6.4 spec, "Number of System Localities" field takes |
| 180 | up 8 bytes. Following that, each matrix entry takes up 1 byte. */ |
| 181 | memset(p, 0, 8 + pds.num_pds * pds.num_pds); |
| 182 | *p = (uint8_t)pds.num_pds; |
| 183 | p += 8; |
| 184 | |
| 185 | for (int i = 0; i < pds.num_pds; i++) { |
| 186 | for (int j = 0; j < pds.num_pds; j++) |
| 187 | p[i * pds.num_pds + j] = pds.pds[i].distances[j]; |
| 188 | } |
| 189 | |
| 190 | current += 8 + pds.num_pds * pds.num_pds; |
| 191 | return current; |
| 192 | } |
| 193 | #else |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 194 | static unsigned long acpi_fill_slit(unsigned long current) |
| 195 | { |
Marc Jones | 70907b0 | 2020-10-28 17:00:31 -0600 | [diff] [blame] | 196 | unsigned int nodes = soc_get_num_cpus(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 197 | |
| 198 | uint8_t *p = (uint8_t *)current; |
| 199 | memset(p, 0, 8 + nodes * nodes); |
| 200 | *p = (uint8_t)nodes; |
| 201 | p += 8; |
| 202 | |
| 203 | /* this assumes fully connected socket topology */ |
| 204 | for (int i = 0; i < nodes; i++) { |
| 205 | for (int j = 0; j < nodes; j++) { |
| 206 | if (i == j) |
| 207 | p[i*nodes+j] = 10; |
| 208 | else |
| 209 | p[i*nodes+j] = 16; |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | current += 8 + nodes * nodes; |
| 214 | return current; |
| 215 | } |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 216 | #endif |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 217 | |
| 218 | /* |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 219 | * This function adds PCIe bridge device entry in DMAR table. If it is called |
| 220 | * in the context of ATSR subtable, it adds ATSR subtable when it is first called. |
| 221 | */ |
| 222 | static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 223 | const struct device *bridge_dev, |
| 224 | uint32_t pcie_seg, |
| 225 | bool is_atsr, bool *first) |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 226 | { |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 227 | const uint32_t bus = bridge_dev->bus->secondary; |
| 228 | const uint32_t dev = PCI_SLOT(bridge_dev->path.pci.devfn); |
| 229 | const uint32_t func = PCI_FUNC(bridge_dev->path.pci.devfn); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 230 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 231 | if (bus == 0) |
| 232 | return current; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 233 | |
| 234 | unsigned long atsr_size = 0; |
| 235 | unsigned long pci_br_size = 0; |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 236 | if (is_atsr == true && first && *first == true) { |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 237 | printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " |
| 238 | "PCI Segment Number: 0x%x\n", 0, pcie_seg); |
| 239 | atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); |
| 240 | *first = false; |
| 241 | } |
| 242 | |
| 243 | printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " |
| 244 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 245 | 0, bus, dev, func); |
| 246 | pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); |
| 247 | |
| 248 | return (atsr_size + pci_br_size); |
| 249 | } |
| 250 | |
| 251 | static unsigned long acpi_create_drhd(unsigned long current, int socket, |
| 252 | int stack, const IIO_UDS *hob) |
| 253 | { |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 254 | unsigned long tmp = current; |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 255 | const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; |
| 256 | const uint32_t bus = ri->BusBase; |
| 257 | const uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 258 | const uint32_t reg_base = ri->VtdBarAddress; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 259 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", |
| 260 | __func__, socket, stack, bus, pcie_seg, reg_base); |
| 261 | |
| 262 | /* Do not generate DRHD for non-PCIe stack */ |
| 263 | if (!reg_base) |
| 264 | return current; |
| 265 | |
Arthur Heymans | a1c4ad3 | 2021-05-04 18:40:28 +0200 | [diff] [blame] | 266 | // Add DRHD Hardware Unit |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 267 | |
| 268 | if (socket == 0 && stack == IioStack0) { |
Arthur Heymans | a1c4ad3 | 2021-05-04 18:40:28 +0200 | [diff] [blame] | 269 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 270 | "Register Base Address: 0x%x\n", |
| 271 | DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); |
| 272 | current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, |
| 273 | pcie_seg, reg_base); |
| 274 | } else { |
| 275 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 276 | "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); |
| 277 | current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); |
| 278 | } |
| 279 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 280 | // Add PCH IOAPIC |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 281 | if (socket == 0 && stack == IioStack0) { |
Arthur Heymans | 6e425e1 | 2020-11-12 21:12:05 +0100 | [diff] [blame] | 282 | union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 283 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
Patrick Rudolph | 57ddd68 | 2023-02-28 09:17:40 +0100 | [diff] [blame] | 284 | "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(VIO_APIC_VADDR), ioapic_bdf.bus, |
| 285 | ioapic_bdf.dev, ioapic_bdf.fn); |
| 286 | current += acpi_create_dmar_ds_ioapic_from_hw(current, |
| 287 | IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 288 | } |
| 289 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 290 | /* SPR has no per stack IOAPIC or CBDMA devices */ |
| 291 | #if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) |
| 292 | uint32_t enum_id; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 293 | // Add IOAPIC entry |
Arthur Heymans | a1cc557 | 2020-11-06 12:53:33 +0100 | [diff] [blame] | 294 | enum_id = soc_get_iio_ioapicid(socket, stack); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 295 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 296 | "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); |
| 297 | current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, |
| 298 | APIC_DEV_NUM, APIC_FUNC_NUM); |
| 299 | |
| 300 | // Add CBDMA devices for CSTACK |
| 301 | if (socket != 0 && stack == CSTACK) { |
| 302 | for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { |
| 303 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 304 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 305 | 0, bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 306 | current += acpi_create_dmar_ds_pci(current, |
| 307 | bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 308 | } |
| 309 | } |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 310 | #endif |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 311 | |
| 312 | // Add PCIe Ports |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 313 | if (socket != 0 || stack != IioStack0) { |
| 314 | struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); |
| 315 | while (dev) { |
| 316 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) |
| 317 | current += |
| 318 | acpi_create_dmar_ds_pci_br_for_port( |
| 319 | current, dev, pcie_seg, false, NULL); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 320 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 321 | dev = dev->sibling; |
| 322 | } |
| 323 | |
| 324 | #if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 325 | // Add VMD |
| 326 | if (hob->PlatformData.VMDStackEnable[socket][stack] && |
| 327 | stack >= PSTACK0 && stack <= PSTACK2) { |
| 328 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 329 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 330 | 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 331 | current += acpi_create_dmar_ds_pci(current, |
| 332 | bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 333 | } |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 334 | #endif |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 335 | } |
| 336 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 337 | #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) |
| 338 | // Add DINO End Points (with memory resources. We don't report every End Point device.) |
| 339 | if (ri->Personality == TYPE_DINO) { |
| 340 | for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { |
| 341 | struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); |
| 342 | while (dev) { |
| 343 | /* This may also require a check for IORESOURCE_PREFETCH, |
| 344 | * but that would not include the FPU (4942/0) */ |
| 345 | if ((dev->resource_list->flags & |
| 346 | (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) == |
| 347 | (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) { |
| 348 | const uint32_t d = PCI_SLOT(dev->path.pci.devfn); |
| 349 | const uint32_t f = PCI_FUNC(dev->path.pci.devfn); |
| 350 | printk(BIOS_DEBUG, " [PCIE Endpoint Device] " |
| 351 | "Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 352 | " PCI Path: 0x%x, 0x%x\n", 0, b, d, f); |
| 353 | current += acpi_create_dmar_ds_pci(current, b, d, f); |
| 354 | } |
| 355 | dev = dev->sibling; |
| 356 | } |
| 357 | } |
| 358 | } |
| 359 | #endif |
| 360 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 361 | // Add HPET |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 362 | if (socket == 0 && stack == IioStack0) { |
Elyes Haouas | 167b7fcd | 2022-12-11 10:38:35 +0100 | [diff] [blame] | 363 | uint16_t hpet_capid = read16p(HPET_BASE_ADDRESS); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 364 | uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count |
| 365 | printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", |
| 366 | __func__, hpet_capid, num_hpets); |
| 367 | //BIT 15 |
| 368 | if (num_hpets && (num_hpets != 0x1f) && |
Elyes Haouas | 167b7fcd | 2022-12-11 10:38:35 +0100 | [diff] [blame] | 369 | (read32p(HPET_BASE_ADDRESS + 0x100) & (0x00008000))) { |
Arthur Heymans | 695dd29 | 2020-11-12 21:05:09 +0100 | [diff] [blame] | 370 | union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 371 | printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " |
| 372 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
Arthur Heymans | 695dd29 | 2020-11-12 21:05:09 +0100 | [diff] [blame] | 373 | 0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn); |
| 374 | current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus, |
| 375 | hpet_bdf.dev, hpet_bdf.fn); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 376 | } |
| 377 | } |
| 378 | |
| 379 | acpi_dmar_drhd_fixup(tmp, current); |
| 380 | |
| 381 | return current; |
| 382 | } |
| 383 | |
| 384 | static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) |
| 385 | { |
| 386 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 387 | uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 388 | unsigned long tmp = current; |
| 389 | bool first = true; |
| 390 | IIO_RESOURCE_INSTANCE iio_resource = |
| 391 | hob->PlatformData.IIO_resource[socket]; |
| 392 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 393 | for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 394 | uint32_t bus = iio_resource.StackRes[stack].BusBase; |
| 395 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 396 | if (!vtd_base) |
| 397 | continue; |
Elyes Haouas | 167b7fcd | 2022-12-11 10:38:35 +0100 | [diff] [blame] | 398 | uint64_t vtd_mmio_cap = read64p(vtd_base + VTD_EXT_CAP_LOW); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 399 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " |
| 400 | "vtd_mmio_cap: 0x%llx\n", |
| 401 | __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); |
| 402 | |
| 403 | // ATSR is applicable only for platform supporting device IOTLBs |
| 404 | // through the VT-d extended capability register |
| 405 | assert(vtd_mmio_cap != 0xffffffffffffffff); |
| 406 | if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 |
| 407 | continue; |
| 408 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 409 | if (bus == 0) |
| 410 | continue; |
| 411 | |
| 412 | struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); |
| 413 | while (dev) { |
| 414 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) |
| 415 | current += |
| 416 | acpi_create_dmar_ds_pci_br_for_port( |
| 417 | current, dev, pcie_seg, true, &first); |
| 418 | |
| 419 | dev = dev->sibling; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 420 | } |
| 421 | } |
| 422 | if (tmp != current) |
| 423 | acpi_dmar_atsr_fixup(tmp, current); |
| 424 | } |
| 425 | |
| 426 | return current; |
| 427 | } |
| 428 | |
| 429 | static unsigned long acpi_create_rmrr(unsigned long current) |
| 430 | { |
| 431 | uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); |
| 432 | |
| 433 | uint32_t *ptr; |
| 434 | |
| 435 | // reserve memory |
| 436 | ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); |
| 437 | if (!ptr) { |
| 438 | ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 439 | assert(ptr); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 440 | memset(ptr, 0, size); |
| 441 | } |
| 442 | |
| 443 | unsigned long tmp = current; |
| 444 | printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " |
| 445 | "End Address (limit): 0x%x\n", |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 446 | 0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1)); |
| 447 | current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr, |
| 448 | (uint32_t)((uint32_t)ptr + size - 1)); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 449 | |
| 450 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 451 | "PCI Path: 0x%x, 0x%x\n", |
| 452 | 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 453 | current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, |
| 454 | PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 455 | |
| 456 | acpi_dmar_rmrr_fixup(tmp, current); |
| 457 | |
| 458 | return current; |
| 459 | } |
| 460 | |
| 461 | static unsigned long acpi_create_rhsa(unsigned long current) |
| 462 | { |
Arthur Heymans | 83b2622 | 2020-11-06 11:50:55 +0100 | [diff] [blame] | 463 | const IIO_UDS *hob = get_iio_uds(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 464 | |
| 465 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 466 | IIO_RESOURCE_INSTANCE iio_resource = |
| 467 | hob->PlatformData.IIO_resource[socket]; |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 468 | for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 469 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 470 | if (!vtd_base) |
| 471 | continue; |
| 472 | |
| 473 | printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " |
| 474 | "Proximity Domain: 0x%x\n", vtd_base, socket); |
| 475 | current += acpi_create_dmar_rhsa(current, vtd_base, socket); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | return current; |
| 480 | } |
| 481 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 482 | /* Skylake-SP doesn't have DINO but not sure how to verify this on CPX */ |
| 483 | #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) |
| 484 | static unsigned long xeonsp_create_satc_dino(unsigned long current, const STACK_RES *ri) |
| 485 | { |
| 486 | for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { |
| 487 | struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); |
| 488 | while (dev) { |
| 489 | if (pciexp_find_extended_cap(dev, PCIE_EXT_CAP_ID_ATS, 0)) { |
| 490 | const uint32_t d = PCI_SLOT(dev->path.pci.devfn); |
| 491 | const uint32_t f = PCI_FUNC(dev->path.pci.devfn); |
| 492 | printk(BIOS_DEBUG, " [SATC Endpoint Device] " |
| 493 | "Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 494 | " PCI Path: 0x%x, 0x%x\n", 0, b, d, f); |
| 495 | current += acpi_create_dmar_ds_pci(current, b, d, f); |
| 496 | } |
| 497 | dev = dev->sibling; |
| 498 | } |
| 499 | } |
| 500 | return current; |
| 501 | } |
| 502 | |
| 503 | /* SoC Integrated Address Translation Cache */ |
| 504 | static unsigned long acpi_create_satc(unsigned long current, const IIO_UDS *hob) |
| 505 | { |
| 506 | |
| 507 | const unsigned long tmp = current; |
| 508 | |
| 509 | // Add the SATC header |
| 510 | current += acpi_create_dmar_satc(current, 0, 0); |
| 511 | |
| 512 | // Find the DINO devices on each socket |
| 513 | for (int socket = (hob->PlatformData.numofIIO - 1); socket >= 0; --socket) { |
| 514 | for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) { |
| 515 | const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; |
| 516 | // Add the DINO ATS devices to the SATC |
| 517 | if (ri->Personality == TYPE_DINO) |
| 518 | current = xeonsp_create_satc_dino(current, ri); |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | acpi_dmar_satc_fixup(tmp, current); |
| 523 | return current; |
| 524 | } |
| 525 | #endif |
| 526 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 527 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 528 | { |
Arthur Heymans | 83b2622 | 2020-11-06 11:50:55 +0100 | [diff] [blame] | 529 | const IIO_UDS *hob = get_iio_uds(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 530 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 531 | // DRHD - socket 0 stack 0 must be the last DRHD entry. |
| 532 | for (int socket = (hob->PlatformData.numofIIO - 1); socket >= 0; --socket) { |
| 533 | for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) |
| 534 | current = acpi_create_drhd(current, socket, stack, hob); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 535 | } |
| 536 | |
| 537 | // RMRR |
| 538 | current = acpi_create_rmrr(current); |
| 539 | |
| 540 | // Root Port ATS Capability |
| 541 | current = acpi_create_atsr(current, hob); |
| 542 | |
| 543 | // RHSA |
| 544 | current = acpi_create_rhsa(current); |
| 545 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 546 | #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) |
| 547 | // SATC |
| 548 | current = acpi_create_satc(current, hob); |
| 549 | #endif |
| 550 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 551 | return current; |
| 552 | } |
| 553 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 554 | unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 555 | struct acpi_rsdp *rsdp) |
| 556 | { |
| 557 | acpi_srat_t *srat; |
| 558 | acpi_slit_t *slit; |
| 559 | acpi_dmar_t *dmar; |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 560 | acpi_hmat_t *hmat; |
| 561 | acpi_cedt_t *cedt; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 562 | |
| 563 | const config_t *const config = config_of(device); |
| 564 | |
| 565 | /* SRAT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 566 | current = ALIGN_UP(current, 8); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 567 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 568 | srat = (acpi_srat_t *)current; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 569 | acpi_create_srat(srat, acpi_fill_srat); |
| 570 | current += srat->header.length; |
| 571 | acpi_add_table(rsdp, srat); |
| 572 | |
| 573 | /* SLIT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 574 | current = ALIGN_UP(current, 8); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 575 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 576 | slit = (acpi_slit_t *)current; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 577 | acpi_create_slit(slit, acpi_fill_slit); |
| 578 | current += slit->header.length; |
| 579 | acpi_add_table(rsdp, slit); |
| 580 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 581 | if (CONFIG(SOC_INTEL_HAS_CXL)) { |
| 582 | /* HMAT*/ |
| 583 | current = ALIGN_UP(current, 8); |
| 584 | printk(BIOS_DEBUG, "ACPI: * HMAT at %lx\n", current); |
| 585 | hmat = (acpi_hmat_t *)current; |
| 586 | acpi_create_hmat(hmat, acpi_fill_hmat); |
| 587 | current += hmat->header.length; |
| 588 | acpi_add_table(rsdp, hmat); |
| 589 | } |
| 590 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 591 | /* DMAR */ |
| 592 | if (config->vtd_support) { |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 593 | current = ALIGN_UP(current, 8); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 594 | dmar = (acpi_dmar_t *)current; |
Marc Jones | b7e591e | 2020-11-13 15:55:31 -0700 | [diff] [blame] | 595 | enum dmar_flags flags = DMAR_INTR_REMAP; |
| 596 | |
| 597 | /* SKX FSP doesn't support X2APIC, but CPX FSP does */ |
| 598 | if (CONFIG(SOC_INTEL_SKYLAKE_SP)) |
| 599 | flags |= DMAR_X2APIC_OPT_OUT; |
| 600 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 601 | printk(BIOS_DEBUG, "ACPI: * DMAR at %lx\n", current); |
Marc Jones | b7e591e | 2020-11-13 15:55:31 -0700 | [diff] [blame] | 602 | printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", flags); |
| 603 | acpi_create_dmar(dmar, flags, acpi_fill_dmar); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 604 | current += dmar->header.length; |
| 605 | current = acpi_align_current(current); |
| 606 | acpi_add_table(rsdp, dmar); |
| 607 | } |
| 608 | |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 609 | if (CONFIG(SOC_INTEL_HAS_CXL)) { |
| 610 | /* CEDT: CXL Early Discovery Table */ |
| 611 | if (get_cxl_node_count() > 0) { |
| 612 | current = ALIGN_UP(current, 8); |
| 613 | printk(BIOS_DEBUG, "ACPI: * CEDT at %lx\n", current); |
| 614 | cedt = (acpi_cedt_t *)current; |
| 615 | acpi_create_cedt(cedt, acpi_fill_cedt); |
| 616 | current += cedt->header.length; |
| 617 | acpi_add_table(rsdp, cedt); |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | if (CONFIG(SOC_ACPI_HEST)) { |
| 622 | printk(BIOS_DEBUG, "ACPI: * HEST at %lx\n", current); |
Rocky Phagura | d4db36e | 2021-04-03 08:49:32 -0700 | [diff] [blame] | 623 | current = hest_create(current, rsdp); |
Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 624 | } |
Rocky Phagura | d4db36e | 2021-04-03 08:49:32 -0700 | [diff] [blame] | 625 | |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 626 | return current; |
| 627 | } |