blob: cc839efc5736219aded590398d2ca404028924b3 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Jonathan Zhang8f895492020-01-16 11:16:45 -08002
3#include <bootblock_common.h>
4#include <device/pci.h>
5#include <FsptUpd.h>
6#include <intelblocks/fast_spi.h>
Johnny Lin6b1e7dd2022-01-24 15:18:57 +08007#include <intelblocks/tco.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -08008#include <soc/iomap.h>
9#include <console/console.h>
Johnny Lin34473ea2020-03-18 10:23:26 +080010#include <cpu/x86/mtrr.h>
Johnny Linebb7f542020-02-19 15:52:45 +080011#include <intelblocks/lpc_lib.h>
Arthur Heymansee55d712021-05-12 16:22:05 +020012#include <security/intel/cbnt/cbnt.h>
Andrey Petrov335384d2020-03-22 22:27:44 -070013#include <soc/pci_devs.h>
Rocky Phagurac62c98a2020-05-23 20:29:00 -070014#include <soc/bootblock.h>
Arthur Heymans087fe9f2020-10-28 14:10:37 +010015#include <fsp/util.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -080016
17const FSPT_UPD temp_ram_init_params = {
18 .FspUpdHeader = {
19 .Signature = FSPT_UPD_SIGNATURE,
20 .Revision = 1,
21 .Reserved = {0},
22 },
23 .FsptCoreUpd = {
24 .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
25 .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
Johnny Lin34473ea2020-03-18 10:23:26 +080026 .CodeRegionBase = (UINT32)CACHE_ROM_BASE,
27 .CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
Jonathan Zhang8f895492020-01-16 11:16:45 -080028 .Reserved1 = {0},
29 },
30 .FsptConfig = {
Jonathan Zhang641642e2020-05-26 13:42:28 -070031 .FsptPort80RouteDisable = 0,
Jonathan Zhang8f895492020-01-16 11:16:45 -080032 .ReservedTempRamInitUpd = {0},
33 },
34 .UnusedUpdSpace0 = {0},
35 .UpdTerminator = 0x55AA,
36};
37
Arthur Heymans02dec122020-11-18 12:27:28 +010038static uint64_t assembly_timestamp;
39static uint64_t bootblock_timestamp;
40
Jonathan Zhang8f895492020-01-16 11:16:45 -080041asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
42{
Arthur Heymans02dec122020-11-18 12:27:28 +010043 /*
44 * FSP-T does not respect its own API and trashes registers
45 * coreboot uses to store its initial timestamp.
46 */
47 assembly_timestamp = base_timestamp;
48 bootblock_timestamp = timestamp_get();
Jonathan Zhang8f895492020-01-16 11:16:45 -080049 fast_spi_cache_bios_region();
50
Arthur Heymans02dec122020-11-18 12:27:28 +010051 bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
Jonathan Zhang8f895492020-01-16 11:16:45 -080052}
53
54void bootblock_soc_early_init(void)
55{
56 fast_spi_early_init(SPI_BASE_ADDRESS);
Johnny Linebb7f542020-02-19 15:52:45 +080057 pch_enable_lpc();
Andrey Petrov335384d2020-03-22 22:27:44 -070058
59 /* Set up P2SB BAR. This is needed for PCR to work */
Nico Huberf4f365f2021-10-14 18:16:39 +020060 uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
61 pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
62 pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
Jonathan Zhang8f895492020-01-16 11:16:45 -080063}
64
65void bootblock_soc_init(void)
66{
Arthur Heymans02dec122020-11-18 12:27:28 +010067 if (assembly_timestamp > bootblock_timestamp)
68 printk(BIOS_WARNING, "Invalid initial timestamp detected\n");
69
Arthur Heymans087fe9f2020-10-28 14:10:37 +010070 if (CONFIG(FSP_CAR))
71 report_fspt_output();
Arthur Heymansee55d712021-05-12 16:22:05 +020072
73 if (CONFIG(INTEL_CBNT_LOGGING))
74 intel_cbnt_log_registers();
75
Rocky Phagurac62c98a2020-05-23 20:29:00 -070076 bootblock_pch_init();
Johnny Lin6b1e7dd2022-01-24 15:18:57 +080077
78 /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
79 tco_configure();
Naresh Solanki08135332022-12-05 11:42:10 +010080
81 report_platform_info();
Jonathan Zhang8f895492020-01-16 11:16:45 -080082}