Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 3 | #include <device/pci_def.h> |
| 4 | #include <intelblocks/cse.h> |
| 5 | #include <intelblocks/smihandler.h> |
| 6 | #include <soc/soc_chip.h> |
| 7 | #include <soc/pci_devs.h> |
| 8 | #include <soc/pm.h> |
| 9 | |
| 10 | /* |
| 11 | * Specific SOC SMI handler during ramstage finalize phase |
| 12 | * |
| 13 | * BIOS can't make CSME function disable as is due to POSTBOOT_SAI |
| 14 | * restriction in place from MCC chipset. Hence create SMI Handler to |
| 15 | * perform CSME function disabling logic during SMM mode. |
| 16 | */ |
| 17 | void smihandler_soc_at_finalize(void) |
| 18 | { |
Subrata Banik | 6fb1267 | 2022-01-03 18:49:35 +0000 | [diff] [blame] | 19 | if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 20 | heci1_disable(); |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 21 | } |
| 22 | |
| 23 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
| 24 | [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, |
| 25 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 26 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 27 | [GPE0_STS_BIT] = smihandler_southbridge_gpe0, |
| 28 | [GPIO_STS_BIT] = smihandler_southbridge_gpi, |
| 29 | [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, |
| 30 | [MCSMI_STS_BIT] = smihandler_southbridge_mc, |
| 31 | #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) |
| 32 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
| 33 | #endif |
| 34 | [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, |
| 35 | [MONITOR_STS_BIT] = smihandler_southbridge_monitor, |
| 36 | }; |