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Angel Pons0612b272020-04-05 15:46:56 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik03e971c2017-03-07 14:02:23 +05302
3#include <cpu/x86/mtrr.h>
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +02004#include <cpu/x86/msr.h>
Subrata Banik03e971c2017-03-07 14:02:23 +05305#include <cpu/x86/cr.h>
6#include <intelblocks/msr.h>
7
8.text
9.global chipset_teardown_car
10chipset_teardown_car:
11
Julius Wernercd49cce2019-03-05 16:53:33 -080012#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbinf8744422018-04-18 16:32:30 -060013 /*
14 * Since Page table is located in CAR, disable paging before CAR
15 * teardown. Also clear CR3 and CR4.PAE.
16 */
17 mov %cr0, %eax
18 and $(~(CR0_PG)), %eax
19 mov %eax, %cr0
20 xor %eax, %eax
21 mov %eax, %cr3
22 mov %cr4, %eax
23 and $(~(CR4_PAE)), %eax
24 mov %eax, %cr4
25#endif
26
Subrata Banik03e971c2017-03-07 14:02:23 +053027 /*
28 * Retrieve return address from stack as it will get trashed below if
29 * execution is utilizing the cache-as-ram stack.
30 */
Patrick Rudolphed5835a2020-11-30 13:53:52 +010031#if ENV_X86_64
32 pop %rbx
33#else
Subrata Banik03e971c2017-03-07 14:02:23 +053034 pop %ebx
Patrick Rudolphed5835a2020-11-30 13:53:52 +010035#endif
Subrata Banik03e971c2017-03-07 14:02:23 +053036
37 /* Disable MTRRs. */
38 mov $(MTRR_DEF_TYPE_MSR), %ecx
39 rdmsr
40 and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
41 wrmsr
42
Julius Wernercd49cce2019-03-05 16:53:33 -080043#if CONFIG(INTEL_CAR_NEM)
Subrata Banik03e971c2017-03-07 14:02:23 +053044.global car_nem_teardown
45car_nem_teardown:
46
47 /* invalidate cache contents. */
48 invd
49
50 /* Knock down bit 1 then bit 0 of NEM control not combining steps. */
51 mov $(MSR_EVICT_CTL), %ecx
52 rdmsr
53 and $(~(1 << 1)), %eax
54 wrmsr
55 and $(~(1 << 0)), %eax
56 wrmsr
57
Julius Wernercd49cce2019-03-05 16:53:33 -080058#elif CONFIG(INTEL_CAR_CQOS)
Subrata Banik03e971c2017-03-07 14:02:23 +053059.global car_cqos_teardown
60car_cqos_teardown:
61
62 /* Go back to all-evicting mode, set both masks to all-1s */
63 mov $MSR_L2_QOS_MASK(0), %ecx
64 rdmsr
65 mov $~0, %al
66 wrmsr
67
68 mov $MSR_L2_QOS_MASK(1), %ecx
69 rdmsr
70 mov $~0, %al
71 wrmsr
72
73 /* Reset CLOS selector to 0 */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020074 mov $IA32_PQR_ASSOC, %ecx
Subrata Banik03e971c2017-03-07 14:02:23 +053075 rdmsr
76 and $~IA32_PQR_ASSOC_MASK, %edx
77 wrmsr
78
Julius Wernercd49cce2019-03-05 16:53:33 -080079#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
Subrata Banik03e971c2017-03-07 14:02:23 +053080.global car_nem_enhanced_teardown
81car_nem_enhanced_teardown:
82
83 /* invalidate cache contents. */
84 invd
85
86 /* Knock down bit 1 then bit 0 of NEM control not combining steps. */
87 mov $(MSR_EVICT_CTL), %ecx
88 rdmsr
89 and $(~(1 << 1)), %eax
90 wrmsr
91 and $(~(1 << 0)), %eax
92 wrmsr
93
94 /* Reset CLOS selector to 0 */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020095 mov $IA32_PQR_ASSOC, %ecx
Subrata Banik03e971c2017-03-07 14:02:23 +053096 rdmsr
97 and $~IA32_PQR_ASSOC_MASK, %edx
98 wrmsr
Subrata Banik0e2510f2021-07-30 17:36:56 +053099#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS)
100 /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */
101 mov $IA32_L3_PROTECTED_WAYS, %ecx
102 xorl %eax, %eax
103 xorl %edx, %edx
104 wrmsr
105#endif
Subrata Banik03e971c2017-03-07 14:02:23 +0530106#endif
107
108 /* Return to caller. */
Patrick Rudolphed5835a2020-11-30 13:53:52 +0100109#if ENV_X86_64
110 jmp *%rbx
111#else
Subrata Banik03e971c2017-03-07 14:02:23 +0530112 jmp *%ebx
Patrick Rudolphed5835a2020-11-30 13:53:52 +0100113#endif