Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_BLOCK_CPU |
| 2 | bool |
| 3 | default n |
| 4 | help |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 5 | This option selects Intel Common CPU Model support code |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 6 | which provides various CPU related APIs which are common |
| 7 | between all Intel Processor families. Common CPU code is supported |
| 8 | for SOCs starting from SKL,KBL,APL, and future. |
| 9 | |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 10 | config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 11 | bool |
| 12 | default n |
| 13 | help |
| 14 | This option selects Intel Common CPU MP Init code. In |
| 15 | this common MP Init mechanism, the MP Init is occurring before |
| 16 | calling FSP Silicon Init. Hence, MP Init will be pulled to |
| 17 | BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is |
| 18 | ensured that all MTRRs are re-programmed based on the DRAM |
| 19 | resource settings. |
| 20 | |
Subrata Banik | a247319 | 2023-02-22 13:03:04 +0000 | [diff] [blame] | 21 | choice |
| 22 | prompt "Application Processors (AP) Feature Programming Configuration to use" |
| 23 | default USE_FSP_FEATURE_PROGRAM_ON_APS if MP_SERVICES_PPI_V1 || MP_SERVICES_PPI_V2 |
| 24 | default USE_COREBOOT_MP_INIT if MP_SERVICES_PPI_V2_NOOP |
| 25 | |
| 26 | config USE_FSP_FEATURE_PROGRAM_ON_APS |
| 27 | bool "Allow FSP running CPU feature programming on MP init" |
| 28 | help |
| 29 | Upon selection, coreboot brings APs from reset and the FSP runs feature programming. |
| 30 | |
| 31 | config USE_COREBOOT_MP_INIT |
| 32 | bool "Use coreboot MP init" |
| 33 | # FSP assumes ownership of the APs (Application Processors) |
| 34 | # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 35 | # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid |
| 36 | # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. |
| 37 | # This will protect APs from getting hijacked by FSP while coreboot |
| 38 | # decides to set SkipMpInit UPD. |
| 39 | select RELOAD_MICROCODE_PATCH |
| 40 | help |
| 41 | Upon selection, coreboot performs MP Init. |
| 42 | |
| 43 | endchoice |
| 44 | |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 45 | config SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| 46 | bool |
| 47 | depends on SOC_INTEL_COMMON_BLOCK_CPU |
| 48 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 49 | config SOC_INTEL_COMMON_BLOCK_CAR |
| 50 | bool |
| 51 | default n |
| 52 | help |
| 53 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 54 | |
| 55 | config INTEL_CAR_NEM |
| 56 | bool |
| 57 | default n |
| 58 | help |
| 59 | Traditionally, CAR is set up by using Non-Evict mode. This method |
| 60 | does not allow CAR and cache to co-exist, because cache fills are |
| 61 | blocked in NEM. |
| 62 | |
| 63 | config INTEL_CAR_CQOS |
| 64 | bool |
| 65 | default n |
| 66 | help |
| 67 | Cache Quality of Service allows more fine-grained control of cache |
| 68 | usage. As result, it is possible to set up a portion of L2 cache for |
| 69 | CAR and use the remainder for actual caching. |
| 70 | |
| 71 | config INTEL_CAR_NEM_ENHANCED |
| 72 | bool |
| 73 | default n |
| 74 | help |
| 75 | A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| 76 | are derived from the requirement to not write out any modified cache line. |
| 77 | With NEM, if there is no physical memory behind the cached area, |
| 78 | the modified data will be lost and NEM results will be inconsistent. |
| 79 | ENHANCED NEM guarantees that modified data is always |
| 80 | kept in cache while clean data is replaced. |
Subrata Banik | 10f5ccf | 2018-12-19 17:49:47 +0530 | [diff] [blame] | 81 | |
Shreesh Chhabbi | 860c684 | 2020-12-03 15:06:20 -0800 | [diff] [blame] | 82 | config CAR_HAS_SF_MASKS |
| 83 | bool |
| 84 | depends on INTEL_CAR_NEM_ENHANCED |
| 85 | help |
| 86 | In the case of non-inclusive cache architecture Snoop Filter MSR |
| 87 | IA32_L3_SF_MASK_x programming is required along with the data ways. |
| 88 | This is applicable for TGL and beyond. |
| 89 | |
Subrata Banik | 16ab9bd | 2021-07-30 17:01:11 +0530 | [diff] [blame] | 90 | config SF_MASK_2WAYS_PER_BIT |
| 91 | bool |
| 92 | depends on INTEL_CAR_NEM_ENHANCED |
| 93 | help |
| 94 | In the case of non-inclusive cache architecture when two ways in |
| 95 | the SF mask are controlled by one bit of the SF QoS register. |
| 96 | This is applicable for TGL alone. |
| 97 | |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 98 | config COS_MAPPED_TO_MSB |
| 99 | bool |
| 100 | depends on INTEL_CAR_NEM_ENHANCED |
| 101 | help |
| 102 | On TGL and JSL platform the class of service configuration |
| 103 | is mapped to MSB of MSR IA32_PQR_ASSOC. |
| 104 | |
Subrata Banik | 0e2510f | 2021-07-30 17:36:56 +0530 | [diff] [blame] | 105 | config CAR_HAS_L3_PROTECTED_WAYS |
| 106 | bool |
| 107 | depends on INTEL_CAR_NEM_ENHANCED |
| 108 | help |
| 109 | On ADL and onwards platform has a newer requirement to protect |
| 110 | L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program |
| 111 | the data ways. |
| 112 | |
Subrata Banik | 10f5ccf | 2018-12-19 17:49:47 +0530 | [diff] [blame] | 113 | config USE_INTEL_FSP_MP_INIT |
| 114 | bool "Perform MP Initialization by FSP" |
| 115 | default n |
Arthur Heymans | b3af349 | 2019-06-10 11:33:40 +0200 | [diff] [blame] | 116 | depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
Subrata Banik | 10f5ccf | 2018-12-19 17:49:47 +0530 | [diff] [blame] | 117 | help |
| 118 | This option allows FSP to perform multiprocessor initialization. |
| 119 | |
| 120 | config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
| 121 | bool "Perform MP Initialization by FSP using coreboot MP PPI service" |
Furquan Shaikh | 5f262be | 2021-02-03 23:10:22 -0800 | [diff] [blame] | 122 | default y if MP_SERVICES_PPI |
Subrata Banik | 10f5ccf | 2018-12-19 17:49:47 +0530 | [diff] [blame] | 123 | default n |
Subrata Banik | 10f5ccf | 2018-12-19 17:49:47 +0530 | [diff] [blame] | 124 | help |
| 125 | This option allows FSP to make use of MP services PPI published by |
| 126 | coreboot to perform multiprocessor initialization. |
Pratik Prajapati | 823e73e | 2020-09-03 11:07:39 -0700 | [diff] [blame] | 127 | |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 128 | config CPU_SUPPORTS_INTEL_TME |
| 129 | bool |
| 130 | default n |
| 131 | help |
| 132 | Select this if the SoC supports Intel Total Memory Encryption (TME). |
| 133 | |
Pratik Prajapati | 823e73e | 2020-09-03 11:07:39 -0700 | [diff] [blame] | 134 | config INTEL_TME |
| 135 | bool "Total Memory Encryption (TME)/Multi-key TME (MKTME)" |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 136 | depends on CPU_SUPPORTS_INTEL_TME |
Angel Pons | 086a91c | 2022-08-15 18:32:00 +0200 | [diff] [blame] | 137 | default y |
Pratik Prajapati | 823e73e | 2020-09-03 11:07:39 -0700 | [diff] [blame] | 138 | help |
| 139 | Enable Total Memory Encryption (TME)/Multi-key TME (MKTME). The spec is |
| 140 | available at "https://software.intel.com/sites/default/files/managed/a5 |
| 141 | /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, |
| 142 | it would get enabled. If CPU supports MKTME, this same config option |
| 143 | enables MKTME. |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 144 | |
Pratikkumar Prajapati | 42f7dc7 | 2023-06-05 18:13:16 -0700 | [diff] [blame] | 145 | config TME_GENERATE_NEW_KEY_ON_WARM_BOOT |
| 146 | bool "Generate new TME key on each warm boot" |
| 147 | depends on INTEL_TME |
| 148 | default n |
| 149 | help |
| 150 | Program Intel TME to generate a new key for each warm boot. TME always |
| 151 | generates a new key on each cold boot. With this option enabled TME |
| 152 | generates a new key even in warm boot. Without this option TME reuses |
| 153 | the key for warm boot. |
| 154 | |
| 155 | config TME_EXCLUDE_CBMEM_ENCRYPTION |
| 156 | bool "Exclude CBMEM from TME encryption" |
| 157 | depends on INTEL_TME |
| 158 | default n |
| 159 | help |
| 160 | This option allows to exclude the CBMEM region from being encrypted by |
| 161 | Intel TME. When TME is enabled it encrypts whole DRAM. TME provides |
| 162 | option to carve out a region of physical memory to get excluded from |
| 163 | encryption. With this config enabled, CBMEM region does not get |
| 164 | encrypted by TME. If TME is not programmed to generate a new key in |
| 165 | warm boot, exclusion range does not need be programmed due to the |
| 166 | fact that TME uses same key in warm boot if |
| 167 | TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed |
| 168 | to generate a new key in warm boot, contents of the CBMEM get |
| 169 | encrypted with a new key in each warm boot case hence, that leads to |
| 170 | loss of CBMEM data from previous warm boot. So enabling this config |
| 171 | allows CBMEM region to get excluded from being encrypted and can be |
| 172 | accessible irrespective of the type of the platform reset. |
| 173 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 174 | config CPU_XTAL_HZ |
| 175 | int |
| 176 | help |
| 177 | Base clock which virtually everything runs on. |
| 178 | |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 179 | config CPU_SUPPORTS_PM_TIMER_EMULATION |
| 180 | bool |
| 181 | default n |
| 182 | help |
| 183 | Select this if the SoC's ucode supports PM ACPI timer emulation (Common |
| 184 | timer Copy), which is required to be able to disable the TCO PM ACPI |
| 185 | timer for power saving. |
Arthur Heymans | 6da7fa2 | 2021-06-23 10:52:01 +0200 | [diff] [blame] | 186 | |
| 187 | config SOC_INTEL_NO_BOOTGUARD_MSR |
| 188 | bool |
| 189 | help |
| 190 | Select this on platforms that do not support Bootguard related MSRs |
| 191 | 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. |
Uwe Poeche | 539fd2a | 2022-03-28 12:39:01 +0200 | [diff] [blame] | 192 | |
| 193 | config SOC_INTEL_DISABLE_POWER_LIMITS |
| 194 | bool |
| 195 | default n |
| 196 | help |
| 197 | Select this if the Running Average Power Limits (RAPL) algorithm |
| 198 | for constant power management is not needed. |
| 199 | |
| 200 | config SOC_INTEL_SET_MIN_CLOCK_RATIO |
| 201 | bool |
| 202 | depends on !SOC_INTEL_DISABLE_POWER_LIMITS |
| 203 | default n |
| 204 | help |
| 205 | If the power budget of the mainboard is limited, it can be useful to |
| 206 | limit the CPU power dissipation at the cost of performance by setting |
| 207 | the lowest possible CPU clock. Enable this option if you need smallest |
| 208 | possible CPU clock. This setting can be overruled by the OS if it has an |
| 209 | p-state driver which can adjust the clock to its need. |
Felix Singer | edb1a40 | 2021-12-30 23:57:58 +0100 | [diff] [blame] | 210 | |
| 211 | config HAVE_HYPERTHREADING |
| 212 | def_bool n |
| 213 | |
| 214 | config FSP_HYPERTHREADING |
| 215 | bool "Enable Hyper-Threading" |
| 216 | depends on HAVE_HYPERTHREADING |
| 217 | default y |
Pratikkumar Prajapati | dd63dc1 | 2022-12-18 18:49:42 -0800 | [diff] [blame] | 218 | |
| 219 | config INTEL_KEYLOCKER |
| 220 | bool "Intel Key Locker" |
| 221 | default n |
| 222 | help |
| 223 | Enable Intel Key Locker if supported by the CPU. Intel Key Locker provides a |
| 224 | mechanism to encrypt and decrypt data with an AES key without having access |
| 225 | to the raw key value by converting AES keys into "handles". The specification |
| 226 | of Key Locker can be found via document #343965 on Intel's site. |
Pratikkumar Prajapati | bd26394 | 2022-12-14 17:11:49 -0800 | [diff] [blame] | 227 | |
| 228 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE |
| 229 | int |
| 230 | depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX_ENABLE |
| 231 | default 256 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB || SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX |
| 232 | default 128 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB |
| 233 | default 64 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB |
| 234 | default 32 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB |
| 235 | default 16 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB |
| 236 | default 8 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB |
| 237 | default 4 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB |
| 238 | default 2 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB |
| 239 | default 0 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB |
| 240 | default 0 |
| 241 | |
| 242 | choice |
| 243 | prompt "PRMRR size" |
| 244 | depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX |
| 245 | default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE |
| 246 | default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && INTEL_KEYLOCKER |
| 247 | default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && !INTEL_KEYLOCKER |
| 248 | help |
| 249 | PRMRR (Protected Memory Range) is the space in RAM that is used to provide a |
| 250 | protected memory area (e.g. for the Intel SGX Secure Enclaves and Intel |
| 251 | Key Locker). The memory region is accessible only by the processor itself to |
| 252 | protect the data from unauthorized access. |
| 253 | |
| 254 | This option allows to select PRMRR size for the intended feature. Depending on |
| 255 | the SoC a lower, compatible value may be chosen at runtime as not all values |
| 256 | are supported on all families. |
| 257 | |
| 258 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX |
| 259 | bool "Maximum" |
| 260 | |
| 261 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB |
| 262 | bool "256 MiB" |
| 263 | |
| 264 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB |
| 265 | bool "128 MiB" |
| 266 | |
| 267 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB |
| 268 | bool "64 MiB" |
| 269 | |
| 270 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB |
| 271 | bool "32 MiB" |
| 272 | |
| 273 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB |
| 274 | bool "16 MiB" |
| 275 | |
| 276 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB |
| 277 | bool "8 MiB" |
| 278 | |
| 279 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB |
| 280 | bool "4 MiB" |
| 281 | |
| 282 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB |
| 283 | bool "2 MiB" |
| 284 | |
| 285 | config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB |
| 286 | bool "0 MiB" |
| 287 | |
| 288 | endchoice |