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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / . / src / soc / intel / cannonlake / uart.c
blob: 99468802634d6503f3536b30321f95ddeee6b54d [file] [log] [blame]
Angel Ponsf5627e82020-04-05 15:46:52 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Andrey Petrovd39c68a2017-06-05 13:26:14 -0700[diff] [blame]2
Michael Niewöhner405f2292020-12-21 03:46:58 +0100[diff] [blame]3#include <commonlib/helpers.h>
Andrey Petrovd39c68a2017-06-05 13:26:14 -0700[diff] [blame]4#include <soc/pci_devs.h>
Andrey Petrovd39c68a2017-06-05 13:26:14 -0700[diff] [blame]5
Michael Niewöhner405f2292020-12-21 03:46:58 +0100[diff] [blame]6const unsigned int uart_devices[] = {
7 PCH_DEVFN_UART0,
8 PCH_DEVFN_UART1,
9 PCH_DEVFN_UART2,
Andrey Petrovd39c68a2017-06-05 13:26:14 -0700[diff] [blame]10};
11
Michael Niewöhner405f2292020-12-21 03:46:58 +0100[diff] [blame]12const int uart_devices_size = ARRAY_SIZE(uart_devices);