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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / . / src / soc / intel / baytrail / chip.h
blob: cf50f1addae461f79e96fc58feca0d549da7fc72 [file] [log] [blame]
Angel Ponsc3f58f62020-04-05 15:46:41 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500[diff] [blame]2
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500[diff] [blame]3/* The devicetree parser expects chip.h to reside directly in the path
4 * specified by the devicetree. */
5
Shawn Nematbakhsh1dbd0e22013-10-28 16:15:02 -0700[diff] [blame]6#ifndef _BAYTRAIL_CHIP_H_
7#define _BAYTRAIL_CHIP_H_
8
Matt DeVillierc72f5f72018-01-28 18:42:10 -0600[diff] [blame]9#include <drivers/intel/gma/i915.h>
Shawn Nematbakhsh1dbd0e22013-10-28 16:15:02 -0700[diff] [blame]10#include <stdint.h>
11
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500[diff] [blame]12struct soc_intel_baytrail_config {
Kein Yuan35110232014-02-22 12:26:55 -0800[diff] [blame]13 uint8_t enable_xdp_tap;
14 uint8_t sata_port_map;
15 uint8_t sata_ahci;
16 uint8_t ide_legacy_combined;
Aaron Durbinae31f7d2013-11-22 14:16:49 -0600[diff] [blame]17 uint8_t clkreq_enable;
Duncan Laurief81a91a2013-11-01 13:32:53 -0700[diff] [blame]18
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800[diff] [blame]19 /* VR low power settings -- enable PS2 mode for gfx and core */
20 int vnn_ps2_enable;
21 int vcc_ps2_enable;
22
23 /* Disable SLP_X stretching after SUS power well loss. */
24 int disable_slp_x_stretch_sus_fail;
25
Duncan Laurief81a91a2013-11-01 13:32:53 -0700[diff] [blame]26 /* USB Port Disable mask */
27 uint16_t usb2_port_disable_mask;
28 uint16_t usb3_port_disable_mask;
29
30 /* USB routing */
31 int usb_route_to_xhci;
Duncan Laurie3c9f1742013-11-01 13:34:00 -0700[diff] [blame]32
33 /* USB PHY settings specific to the board */
34 uint32_t usb2_per_port_lane0;
35 uint32_t usb2_per_port_rcomp_hs_pullup0;
36 uint32_t usb2_per_port_lane1;
37 uint32_t usb2_per_port_rcomp_hs_pullup1;
38 uint32_t usb2_per_port_lane2;
39 uint32_t usb2_per_port_rcomp_hs_pullup2;
40 uint32_t usb2_per_port_lane3;
41 uint32_t usb2_per_port_rcomp_hs_pullup3;
Kane Chen314c4c32014-07-17 09:51:50 -0700[diff] [blame]42 uint32_t usb2_comp_bg;
Aaron Durbin8cbf47f2013-12-04 11:03:20 -0600[diff] [blame]43
44 /* LPE Audio Clock configuration. */
45 int lpe_codec_clk_freq; /* 19 or 25 are valid. */
46 int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
Aaron Durbin8b120a82013-12-10 08:35:51 -0800[diff] [blame]47
48 /* Native SD Card controller - override controller capabilities. */
49 uint32_t sdcard_cap_low;
50 uint32_t sdcard_cap_high;
Duncan Laurieb40e4442013-12-09 14:38:57 -0800[diff] [blame]51
Duncan Laurie430bf0d2013-12-10 14:37:42 -0800[diff] [blame]52 /* Enable devices in ACPI mode */
53 int lpss_acpi_mode;
54 int scc_acpi_mode;
55 int lpe_acpi_mode;
56
Kein Yuan35110232014-02-22 12:26:55 -0800[diff] [blame]57 /* Allow PCIe devices to wake system from suspend. */
58 int pcie_wake_enable;
59
Jacob Garber767c4b22019-07-22 13:31:38 -0600[diff] [blame]60 uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
Duncan Laurieb40e4442013-12-09 14:38:57 -0800[diff] [blame]61 uint16_t gpu_pipea_power_on_delay;
62 uint16_t gpu_pipea_light_on_delay;
63 uint16_t gpu_pipea_power_off_delay;
64 uint16_t gpu_pipea_light_off_delay;
65 uint16_t gpu_pipea_power_cycle_delay;
Aaron Durbin59e209a2014-04-24 11:35:28 -0500[diff] [blame]66 int gpu_pipea_pwm_freq_hz;
Duncan Laurieb40e4442013-12-09 14:38:57 -0800[diff] [blame]67
Jacob Garber767c4b22019-07-22 13:31:38 -0600[diff] [blame]68 uint8_t gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
Duncan Laurieb40e4442013-12-09 14:38:57 -0800[diff] [blame]69 uint16_t gpu_pipeb_power_on_delay;
70 uint16_t gpu_pipeb_light_on_delay;
71 uint16_t gpu_pipeb_power_off_delay;
72 uint16_t gpu_pipeb_light_off_delay;
73 uint16_t gpu_pipeb_power_cycle_delay;
Aaron Durbin59e209a2014-04-24 11:35:28 -0500[diff] [blame]74 int gpu_pipeb_pwm_freq_hz;
Kane Chenba9b7bf2015-01-17 08:19:54 +0800[diff] [blame]75 int disable_ddr_2x_refresh_rate;
Matt DeVillierc72f5f72018-01-28 18:42:10 -0600[diff] [blame]76
77 struct i915_gpu_controller_info gfx;
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500[diff] [blame]78};
79
Aaron Durbin9a7d7bc2013-09-07 00:41:48 -0500[diff] [blame]80#endif /* _BAYTRAIL_CHIP_H_ */