blob: fb2f7acd916d0bac47bc90091b3a3f5ebadae8b6 [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Jones24484842017-05-04 21:17:45 -06002
Marc Jones24484842017-05-04 21:17:45 -06003#include <device/device.h>
Marc Jones24484842017-05-04 21:17:45 -06004#include <device/pci.h>
Marc Jones24484842017-05-04 21:17:45 -06005#include <device/pci_ops.h>
Marshall Dawsonaa67def2019-05-03 16:10:34 -06006#include <amdblocks/sata.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -06007#include <soc/southbridge.h>
Marc Jones24484842017-05-04 21:17:45 -06008
Marshall Dawsonaa67def2019-05-03 16:10:34 -06009void soc_enable_sata_features(struct device *dev)
Marc Jones24484842017-05-04 21:17:45 -060010{
Marshall Dawson25e54012019-05-29 09:29:12 -060011 u8 *ahci_ptr;
12 u32 misc_ctl, cap_cfg;
Marc Jones24484842017-05-04 21:17:45 -060013
Marc Jones24484842017-05-04 21:17:45 -060014 u32 temp;
15
16 /* unlock the write-protect */
Marshall Dawson25e54012019-05-29 09:29:12 -060017 misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
18 misc_ctl |= SATA_MISC_SUBCLASS_WREN;
19 pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
Marc Jones24484842017-05-04 21:17:45 -060020
21 /* set the SATA AHCI mode to allow port expanders */
Marshall Dawson25e54012019-05-29 09:29:12 -060022 ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
23 pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
24
25 cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
26 cap_cfg |= SATA_CAPABILITY_SPM;
27 write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
Marc Jones24484842017-05-04 21:17:45 -060028
29 /* lock the write-protect */
Marshall Dawson25e54012019-05-29 09:29:12 -060030 temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
31 temp &= ~SATA_MISC_SUBCLASS_WREN;
32 pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
Marc Jones24484842017-05-04 21:17:45 -060033};