Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 3 | #include <amdblocks/gpio.h> |
| 4 | #include <amdblocks/uart.h> |
| 5 | #include <commonlib/helpers.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 6 | #include <device/mmio.h> |
Elyes Haouas | 5e2602a | 2023-01-14 05:46:25 +0100 | [diff] [blame] | 7 | #include <gpio.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 8 | #include <soc/aoac_defs.h> |
Felix Held | c6e4cc8 | 2022-10-18 19:22:21 +0200 | [diff] [blame] | 9 | #include <soc/iomap.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 10 | #include <soc/southbridge.h> |
| 11 | #include <soc/uart.h> |
| 12 | #include <types.h> |
| 13 | |
Felix Held | d2ebe16 | 2022-10-18 18:16:14 +0200 | [diff] [blame] | 14 | static const struct soc_uart_ctrlr_info uart_info[] = { |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 15 | [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 16 | PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), |
| 17 | PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 18 | } }, |
| 19 | [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 20 | PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), |
| 21 | PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 22 | } }, |
| 23 | [2] = { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 24 | PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), |
| 25 | PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 26 | } }, |
| 27 | [3] = { APU_UART3_BASE, FCH_AOAC_DEV_UART3, "FUR3", { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 28 | PAD_NF(GPIO_135, UART3_TXD, PULL_NONE), |
| 29 | PAD_NF(GPIO_137, UART3_RXD, PULL_NONE), |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 30 | } }, |
| 31 | [4] = { APU_UART4_BASE, FCH_AOAC_DEV_UART4, "FUR4", { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 32 | PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), |
| 33 | PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), |
Felix Held | fb8c78b | 2022-10-18 18:40:16 +0200 | [diff] [blame] | 34 | } }, |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 35 | }; |
| 36 | |
Felix Held | 97e6125 | 2022-10-18 19:03:20 +0200 | [diff] [blame] | 37 | const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 38 | { |
Felix Held | 957e232 | 2022-10-18 20:22:24 +0200 | [diff] [blame] | 39 | *num_ctrlrs = ARRAY_SIZE(uart_info); |
| 40 | return uart_info; |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | void clear_uart_legacy_config(void) |
| 44 | { |
| 45 | write16p(FCH_LEGACY_UART_DECODE, 0); |
| 46 | } |