Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: BSD-3-Clause |
| 2 | |
| 3 | # TODO: Move as much as possible to common |
| 4 | # TODO: Update for Glinda |
| 5 | |
| 6 | ifeq ($(CONFIG_SOC_AMD_GLINDA),y) |
| 7 | |
| 8 | subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage |
| 9 | |
| 10 | # Beware that all-y also adds the compilation unit to verstage on PSP |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 11 | all-y += aoac.c |
Felix Held | 46cd1b5 | 2023-04-01 01:21:27 +0200 | [diff] [blame] | 12 | all-y += config.c |
| 13 | all-y += i2c.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 14 | |
Felix Held | f008e0a | 2023-04-01 01:31:24 +0200 | [diff] [blame] | 15 | # all_x86-y adds the compilation unit to all stages that run on the x86 cores |
| 16 | all_x86-y += gpio.c |
| 17 | all_x86-y += uart.c |
| 18 | |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 19 | bootblock-y += early_fch.c |
| 20 | bootblock-y += espi_util.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 21 | |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 22 | verstage-y += espi_util.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 23 | |
| 24 | romstage-y += fsp_m_params.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 25 | romstage-y += romstage.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 26 | |
| 27 | ramstage-y += acpi.c |
| 28 | ramstage-y += agesa_acpi.c |
| 29 | ramstage-y += chip.c |
| 30 | ramstage-y += cpu.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 31 | ramstage-y += fch.c |
| 32 | ramstage-y += fsp_s_params.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 33 | ramstage-y += mca.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 34 | ramstage-y += root_complex.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 35 | ramstage-y += xhci.c |
| 36 | |
| 37 | smm-y += gpio.c |
| 38 | smm-y += smihandler.c |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 39 | smm-$(CONFIG_DEBUG_SMI) += uart.c |
| 40 | |
| 41 | CPPFLAGS_common += -I$(src)/soc/amd/glinda/include |
| 42 | CPPFLAGS_common += -I$(src)/soc/amd/glinda/acpi |
| 43 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/glinda |
| 44 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common |
| 45 | |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 46 | # ROMSIG Normally At ROMBASE + 0x20000 |
| 47 | # Overridden by CONFIG_AMD_FWM_POSITION_INDEX |
| 48 | # +-----------+---------------+----------------+------------+ |
| 49 | # |0x55AA55AA | | | | |
| 50 | # +-----------+---------------+----------------+------------+ |
| 51 | # | | PSPDIR ADDR | BIOSDIR ADDR | |
| 52 | # +-----------+---------------+----------------+ |
| 53 | |
| 54 | $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ |
| 55 | $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) |
| 56 | |
Martin Roth | b486fe9 | 2023-01-09 21:21:48 -0700 | [diff] [blame] | 57 | # Fixed EFS location |
| 58 | GLINDA_FWM_POSITION=0xff020000 |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 59 | |
| 60 | # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes |
| 61 | # Building the cbfs image will fail if the offset isn't large enough |
| 62 | AMD_FW_AB_POSITION := 0x40 |
| 63 | |
| 64 | GLINDA_FW_A_POSITION=$(call int-add, \ |
| 65 | $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ |
| 66 | $(AMD_FW_AB_POSITION)) |
| 67 | |
| 68 | GLINDA_FW_B_POSITION=$(call int-add, \ |
| 69 | $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ |
| 70 | $(AMD_FW_AB_POSITION)) |
| 71 | # |
| 72 | # PSP Directory Table items |
| 73 | # |
| 74 | # Certain ordering requirements apply, however these are ensured by amdfwtool. |
| 75 | # For more information see "AMD Platform Security Processor BIOS Architecture |
| 76 | # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). |
| 77 | # |
| 78 | |
| 79 | ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) |
| 80 | PSP_SOFTFUSE_BITS += 7 |
| 81 | endif |
| 82 | |
| 83 | ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) |
| 84 | # Enable secure debug unlock |
| 85 | PSP_SOFTFUSE_BITS += 0 |
| 86 | OPT_TOKEN_UNLOCK="--token-unlock" |
| 87 | endif |
| 88 | |
| 89 | ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) |
| 90 | OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" |
| 91 | else |
| 92 | # Disable MP2 firmware loading |
| 93 | PSP_SOFTFUSE_BITS += 29 |
| 94 | endif |
| 95 | |
| 96 | # Use additional Soft Fuse bits specified in Kconfig |
| 97 | PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) |
| 98 | |
| 99 | # type = 0x3a |
| 100 | ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) |
| 101 | PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) |
| 102 | endif |
| 103 | |
| 104 | # type = 0x55 |
| 105 | ifeq ($(CONFIG_HAVE_SPL_FILE),y) |
| 106 | SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
| 107 | ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) |
| 108 | SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) |
| 109 | else |
| 110 | SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
| 111 | endif |
| 112 | endif |
| 113 | |
| 114 | # |
| 115 | # BIOS Directory Table items - proper ordering is managed by amdfwtool |
| 116 | # |
| 117 | |
| 118 | # type = 0x60 |
| 119 | PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) |
| 120 | |
| 121 | # type = 0x61 |
| 122 | PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) |
| 123 | |
| 124 | # type = 0x62 |
| 125 | PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img |
| 126 | PSP_ELF_FILE=$(objcbfs)/bootblock.elf |
Felix Held | 3b89c95 | 2022-11-22 20:02:46 +0100 | [diff] [blame] | 127 | PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') |
| 128 | PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 129 | |
| 130 | # type = 0x63 - construct APOB NV base/size from flash map |
| 131 | # The flashmap section used for this is expected to be named RW_MRC_CACHE |
| 132 | APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) |
| 133 | APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) |
| 134 | |
| 135 | ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) |
| 136 | # type = 0x6B - PSP Shared memory location |
| 137 | ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) |
| 138 | PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) |
| 139 | PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) |
| 140 | endif |
| 141 | |
| 142 | # type = 0x52 - PSP Bootloader Userspace Application (verstage) |
| 143 | PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) |
| 144 | PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) |
| 145 | endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 146 | |
| 147 | ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) |
| 148 | SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ |
| 149 | $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ |
| 150 | $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) |
| 151 | SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ |
| 152 | $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ |
| 153 | $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) |
| 154 | SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed |
| 155 | SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed |
| 156 | endif # CONFIG_SEPARATE_SIGNED_PSPFW |
| 157 | |
| 158 | # Helper function to return a value with given bit set |
| 159 | # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. |
| 160 | set-bit=$(call int-shift-left, 1 $(call _toint,$1)) |
| 161 | PSP_SOFTFUSE=$(shell A=$(call int-add, \ |
| 162 | $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) |
| 163 | |
| 164 | # |
| 165 | # Build the arguments to amdfwtool (order is unimportant). Missing file names |
| 166 | # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. |
| 167 | # |
| 168 | |
| 169 | add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) |
| 170 | |
| 171 | OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) |
| 172 | OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) |
| 173 | |
| 174 | OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ |
| 175 | $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ |
| 176 | $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) |
| 177 | |
| 178 | OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) |
| 179 | OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) |
| 180 | OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) |
| 181 | OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) |
| 182 | |
| 183 | OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) |
| 184 | OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) |
| 185 | OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) |
| 186 | OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) |
| 187 | OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) |
| 188 | OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) |
| 189 | OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) |
| 190 | |
| 191 | OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) |
| 192 | OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) |
| 193 | OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) |
| 194 | OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) |
| 195 | |
| 196 | OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) |
| 197 | |
| 198 | OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) |
| 199 | OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) |
| 200 | OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) |
| 201 | |
| 202 | # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant |
| 203 | OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) |
| 204 | |
| 205 | AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ |
| 206 | $(OPT_APOB_ADDR) \ |
Martin Roth | 0acf59d | 2023-03-08 15:18:24 -0700 | [diff] [blame] | 207 | $(OPT_DEBUG_AMDFWTOOL) \ |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 208 | $(OPT_PSP_BIOSBIN_FILE) \ |
| 209 | $(OPT_PSP_BIOSBIN_DEST) \ |
| 210 | $(OPT_PSP_BIOSBIN_SIZE) \ |
| 211 | $(OPT_PSP_SOFTFUSE) \ |
| 212 | $(OPT_PSP_LOAD_MP2_FW) \ |
| 213 | --use-pspsecureos \ |
| 214 | --load-s0i3 \ |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 215 | $(OPT_TOKEN_UNLOCK) \ |
| 216 | $(OPT_WHITELIST_FILE) \ |
| 217 | $(OPT_PSP_SHAREDMEM_BASE) \ |
| 218 | $(OPT_PSP_SHAREDMEM_SIZE) \ |
| 219 | $(OPT_EFS_SPI_READ_MODE) \ |
| 220 | $(OPT_EFS_SPI_SPEED) \ |
| 221 | $(OPT_EFS_SPI_MICRON_FLAG) \ |
| 222 | --config $(CONFIG_AMDFW_CONFIG_FILE) \ |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 223 | --flashsize $(CONFIG_ROM_SIZE) \ |
| 224 | $(OPT_RECOVERY_AB_SINGLE_COPY) |
| 225 | |
| 226 | $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ |
| 227 | $(PSP_VERSTAGE_FILE) \ |
| 228 | $(PSP_VERSTAGE_SIG_FILE) \ |
| 229 | $$(PSP_APCB_FILES) \ |
| 230 | $(DEP_FILES) \ |
| 231 | $(AMDFWTOOL) \ |
| 232 | $(obj)/fmap_config.h \ |
| 233 | $(objcbfs)/bootblock.elf # this target also creates the .map file |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 234 | rm -f $@ |
| 235 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 236 | $(AMDFWTOOL) \ |
| 237 | $(AMDFW_COMMON_ARGS) \ |
| 238 | $(OPT_APOB_NV_SIZE) \ |
| 239 | $(OPT_APOB_NV_BASE) \ |
| 240 | $(OPT_VERSTAGE_FILE) \ |
| 241 | $(OPT_VERSTAGE_SIG_FILE) \ |
| 242 | $(OPT_SPL_TABLE_FILE) \ |
| 243 | --location $(shell printf "%#x" $(GLINDA_FWM_POSITION)) \ |
| 244 | --output $@ |
| 245 | |
| 246 | $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) |
| 247 | rm -f $@ |
| 248 | @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" |
| 249 | $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ |
| 250 | --maxsize $(PSP_BIOSBIN_SIZE) |
| 251 | |
| 252 | $(obj)/amdfw_a.rom: $(obj)/amdfw.rom |
| 253 | rm -f $@ |
| 254 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 255 | $(AMDFWTOOL) \ |
| 256 | $(AMDFW_COMMON_ARGS) \ |
| 257 | $(OPT_APOB_NV_SIZE) \ |
| 258 | $(OPT_APOB_NV_BASE) \ |
| 259 | $(OPT_SPL_RW_AB_TABLE_FILE) \ |
| 260 | $(OPT_SIGNED_AMDFW_A_POSITION) \ |
| 261 | $(OPT_SIGNED_AMDFW_A_FILE) \ |
| 262 | --location $(shell printf "%#x" $(GLINDA_FW_A_POSITION)) \ |
| 263 | --anywhere \ |
| 264 | --output $@ |
| 265 | |
| 266 | $(obj)/amdfw_b.rom: $(obj)/amdfw.rom |
| 267 | rm -f $@ |
| 268 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 269 | $(AMDFWTOOL) \ |
| 270 | $(AMDFW_COMMON_ARGS) \ |
| 271 | $(OPT_APOB_NV_SIZE) \ |
| 272 | $(OPT_APOB_NV_BASE) \ |
| 273 | $(OPT_SPL_RW_AB_TABLE_FILE) \ |
| 274 | $(OPT_SIGNED_AMDFW_B_POSITION) \ |
| 275 | $(OPT_SIGNED_AMDFW_B_FILE) \ |
| 276 | --location $(shell printf "%#x" $(GLINDA_FW_B_POSITION)) \ |
| 277 | --anywhere \ |
| 278 | --output $@ |
| 279 | |
| 280 | |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 281 | ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) |
| 282 | cbfs-files-y += apu/amdfw_a |
| 283 | apu/amdfw_a-file := $(obj)/amdfw_a.rom |
| 284 | apu/amdfw_a-position := $(AMD_FW_AB_POSITION) |
| 285 | apu/amdfw_a-type := raw |
| 286 | |
| 287 | cbfs-files-y += apu/amdfw_b |
| 288 | apu/amdfw_b-file := $(obj)/amdfw_b.rom |
| 289 | apu/amdfw_b-position := $(AMD_FW_AB_POSITION) |
| 290 | apu/amdfw_b-type := raw |
| 291 | |
| 292 | ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) |
| 293 | build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom |
| 294 | @printf " Adding Signed ROM and HASH\n" |
| 295 | $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed |
| 296 | $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed |
| 297 | $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ |
| 298 | -n apu/amdfw_a_hash -t raw |
| 299 | $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ |
| 300 | -n apu/amdfw_b_hash -t raw |
| 301 | endif # CONFIG_SEPARATE_SIGNED_PSPFW |
| 302 | endif |
| 303 | |
| 304 | endif # ($(CONFIG_SOC_AMD_GLINDA),y) |