Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H |
| 4 | #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H |
| 5 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 6 | /* Device 0:0.0 PCI configuration space */ |
| 7 | |
Eran Mitrani | 400c300 | 2022-05-25 16:29:19 -0700 | [diff] [blame^] | 8 | |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 9 | /* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 10 | #define DPR 0x5c |
| 11 | #define DPR_EPM (1 << 2) |
| 12 | #define DPR_PRS (1 << 1) |
| 13 | #define DPR_SIZE_MASK 0xff0 |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 14 | /* CAPID0_A */ |
| 15 | #define CAPID_ECCDIS (1 << 25) |
| 16 | #define CAPID_DDPCD (1 << 14) |
| 17 | #define CAPID_PDCD (1 << 12) |
| 18 | #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 19 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 20 | #define PAM0 0x80 |
| 21 | #define PAM1 0x81 |
| 22 | #define PAM2 0x82 |
| 23 | #define PAM3 0x83 |
| 24 | #define PAM4 0x84 |
| 25 | #define PAM5 0x85 |
| 26 | #define PAM6 0x86 |
| 27 | |
Tim Wawrzynczak | d87af79 | 2021-08-24 09:20:14 -0600 | [diff] [blame] | 28 | /* PAM0 contains the lock bit */ |
| 29 | #define PAM_LOCK (1 << 0) |
| 30 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 31 | /* Device 0:0.0 MMIO space */ |
| 32 | #define MCH_PAIR 0x5418 |
| 33 | |
| 34 | /* |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 35 | * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC. |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 36 | * |
| 37 | * IMR registers are found under MCHBAR. |
| 38 | */ |
| 39 | #define MCH_IMR0_BASE 0x6870 |
| 40 | #define MCH_IMR0_MASK 0x6874 |
| 41 | #define MCH_IMR_PITCH 0x20 |
| 42 | #define MCH_NUM_IMRS 20 |
| 43 | |
| 44 | /* |
| 45 | * System Memory Map Registers |
| 46 | * - top_of_ram -> TSEG - DPR: uncacheable |
| 47 | * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved |
| 48 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 49 | * - 4GiB -> TOUUD: cacheable |
| 50 | */ |
| 51 | enum { |
| 52 | SA_TOUUD_REG, |
| 53 | SA_TOLUD_REG, |
| 54 | SA_BGSM_REG, |
| 55 | SA_TSEG_REG, |
| 56 | /* Must be last. */ |
| 57 | MAX_MAP_ENTRIES |
| 58 | }; |
| 59 | |
| 60 | /* |
| 61 | * Set Fixed MMIO range |
| 62 | * REG = Either PCI configuration space registers. |
| 63 | * IS_64_BIT = If registers/offset is 64 bit. |
| 64 | * DESCRIPTION = Name of the register/offset. |
| 65 | */ |
| 66 | struct sa_mem_map_descriptor { |
| 67 | unsigned int reg; |
| 68 | bool is_64_bit; |
| 69 | const char *description; |
| 70 | }; |
| 71 | |
| 72 | #endif /* SOC_INTEL_COMMON_BLOCK_SA_DEF_H */ |