Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * Copyright 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <arch/cache.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 19 | #include <cpu/cpu.h> |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 20 | #include <bootmode.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 21 | #include <bootstate.h> |
| 22 | #include <cbmem.h> |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <soc/nvidia/tegra/dc.h> |
| 26 | #include <soc/addressmap.h> |
| 27 | #include <soc/clock.h> |
| 28 | #include <soc/cpu.h> |
| 29 | #include <soc/mc.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 30 | #include <soc/nvidia/tegra/apbmisc.h> |
| 31 | #include <string.h> |
| 32 | #include <timer.h> |
Yen Lin | ae3d71a | 2015-06-01 15:32:09 -0700 | [diff] [blame] | 33 | #include <soc/sdram.h> |
| 34 | #include <soc/sdram_configs.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 35 | |
| 36 | #include "chip.h" |
| 37 | |
| 38 | static void soc_read_resources(device_t dev) |
| 39 | { |
| 40 | unsigned long index = 0; |
| 41 | int i; uintptr_t begin, end; |
| 42 | size_t size; |
| 43 | |
| 44 | for (i = 0; i < CARVEOUT_NUM; i++) { |
| 45 | carveout_range(i, &begin, &size); |
| 46 | if (size == 0) |
| 47 | continue; |
| 48 | reserved_ram_resource(dev, index++, begin * KiB, size * KiB); |
| 49 | } |
| 50 | |
| 51 | memory_in_range_below_4gb(&begin, &end); |
| 52 | size = end - begin; |
| 53 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 54 | |
| 55 | memory_in_range_above_4gb(&begin, &end); |
| 56 | size = end - begin; |
| 57 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 58 | } |
| 59 | |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 60 | static struct device_operations soc_ops = { |
| 61 | .read_resources = soc_read_resources, |
| 62 | .set_resources = DEVICE_NOOP, |
| 63 | .enable_resources = DEVICE_NOOP, |
| 64 | .init = DEVICE_NOOP, |
| 65 | .scan_bus = NULL, |
| 66 | }; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 67 | |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 68 | static void enable_tegra210_dev(device_t dev) |
| 69 | { |
| 70 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 71 | dev->ops = &soc_ops; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 72 | |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 73 | if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) |
| 74 | return; |
| 75 | |
| 76 | if (display_init_required()) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 77 | display_startup(dev); |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 78 | else |
| 79 | printk(BIOS_INFO, "Skipping display init.\n"); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 80 | } |
| 81 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 82 | static void tegra210_init(void *chip_info) |
| 83 | { |
| 84 | struct tegra_revision rev; |
| 85 | |
| 86 | tegra_revision_info(&rev); |
| 87 | |
| 88 | printk(BIOS_INFO, "chip %x rev %02x.%x\n", |
| 89 | rev.chip_id, rev.major, rev.minor); |
Yen Lin | ae3d71a | 2015-06-01 15:32:09 -0700 | [diff] [blame] | 90 | |
| 91 | /* Save sdram parameters to scratch regs to be used in LP0 resume */ |
| 92 | sdram_lp0_save_params(get_sdram_config()); |
| 93 | printk(BIOS_INFO, "sdram params saved.\n"); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | struct chip_operations soc_nvidia_tegra210_ops = { |
| 97 | CHIP_NAME("SOC Nvidia Tegra210") |
| 98 | .init = tegra210_init, |
| 99 | .enable_dev = enable_tegra210_dev, |
| 100 | }; |
| 101 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 102 | static void enable_plld(void *unused) |
| 103 | { |
| 104 | /* |
| 105 | * Configure a conservative 300MHz clock for PLLD. The kernel cannot |
| 106 | * handle PLLD not being configured so enable PLLD unconditionally |
| 107 | * with a default clock rate. |
| 108 | */ |
| 109 | clock_configure_plld(300 * MHz); |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init() |
| 114 | * is the first thing called. This ensures PLLD is up and functional before |
| 115 | * anything that mainboard can do that implicitly relies on PLLD. |
| 116 | */ |
| 117 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL); |