Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de> |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 5 | * Copyright (C) 2017 Keith Hui <buurin@gmail.com> |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame] | 17 | #include <southbridge/intel/i82371eb/i82371eb.h> |
Tobias Diedrich | ca6d808 | 2010-11-29 20:40:33 +0000 | [diff] [blame] | 18 | |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 19 | #define SUPERIO_PNP_BASE 0x3F0 |
| 20 | #define SUPERIO_SHOW_UARTA |
| 21 | #define SUPERIO_SHOW_UARTB |
| 22 | #define SUPERIO_SHOW_FDC |
| 23 | #define SUPERIO_SHOW_LPT |
| 24 | |
Elyes HAOUAS | 6d19a20 | 2018-11-22 11:15:29 +0100 | [diff] [blame] | 25 | #include <arch/acpi.h> |
| 26 | DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 27 | { |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 28 | /* \_PR scope defining the main processor is generated in SSDT. */ |
| 29 | |
| 30 | OperationRegion(X80, SystemIO, 0x80, 1) |
| 31 | Field(X80, ByteAcc, NoLock, Preserve) |
| 32 | { |
| 33 | P80, 8 |
| 34 | } |
| 35 | |
| 36 | /* |
| 37 | * For now only define 2 power states: |
| 38 | * - S0 which is fully on |
| 39 | * - S5 which is soft off |
| 40 | * Any others would involve declaring the wake up methods. |
| 41 | */ |
| 42 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 43 | /* |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 44 | * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 |
| 45 | * |
| 46 | * 0: soft off/suspend to disk S5 |
| 47 | * 1: suspend to ram S3 |
| 48 | * 2: powered on suspend, context lost S2 |
| 49 | * Note: 'context lost' means the CPU restarts at the reset |
| 50 | * vector |
| 51 | * 3: powered on suspend, CPU context lost S1 |
| 52 | * Note: Looks like 'CPU context lost' does _not_ mean the |
| 53 | * CPU restarts at the reset vector. Most likely only |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 54 | * caches are lost, so both 0x3 and 0x4 map to ACPI S1 |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 55 | * 4: powered on suspend, context maintained S1 |
| 56 | * 5: working (clock control) S0 |
| 57 | * 6: reserved |
| 58 | * 7: reserved |
| 59 | */ |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 60 | Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) |
| 61 | Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) |
| 62 | Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) |
| 63 | |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 64 | OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) |
| 65 | Field (GPOB, ByteAcc, NoLock, Preserve) |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 66 | { |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 67 | Offset (0x03), |
| 68 | TO12, 1, /* Device trap 12 */ |
| 69 | Offset (0x08), |
| 70 | FANM, 1, /* GPO0, meant for fan */ |
| 71 | Offset (0x09), |
| 72 | PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ |
| 73 | , 3, /* this goes low when power is cut from its core. */ |
| 74 | , 2, |
| 75 | , 16, |
| 76 | MSG0, 1 /* GPO30, message LED */ |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 77 | } |
| 78 | |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 79 | /* Prepare To Sleep, Arg0 is target S-state */ |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 80 | Method (\_PTS, 1, NotSerialized) |
| 81 | { |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 82 | /* Disable fan, blink power LED, if not turning off */ |
| 83 | If (LNotEqual (Arg0, 0x05)) |
| 84 | { |
| 85 | Store (Zero, FANM) |
| 86 | Store (Zero, PLED) |
| 87 | } |
| 88 | |
| 89 | /* Arms SMI for device 12 */ |
| 90 | Store (One, TO12) |
| 91 | /* Put out a POST code */ |
| 92 | Or (Arg0, 0xF0, P80) |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | Method (\_WAK, 1, NotSerialized) |
| 96 | { |
| 97 | /* Re-enable fan, stop power led blinking */ |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 98 | Store (One, FANM) |
Tobias Diedrich | 4e22a3b | 2010-12-13 22:39:46 +0100 | [diff] [blame] | 99 | Store (One, PLED) |
| 100 | /* wake OK */ |
| 101 | Return(Package(0x02){0x00, 0x00}) |
| 102 | } |
| 103 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 104 | /* Root of the bus hierarchy */ |
| 105 | Scope (\_SB) |
| 106 | { |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 107 | Device (PWRB) |
| 108 | { |
| 109 | /* Power Button Device */ |
| 110 | Name (_HID, EisaId ("PNP0C0C")) |
| 111 | Method (_STA, 0, NotSerialized) |
| 112 | { |
| 113 | Return (0x0B) |
| 114 | } |
| 115 | } |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 116 | #include <southbridge/intel/i82371eb/acpi/intx.asl> |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 117 | |
| 118 | PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) |
| 119 | PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) |
| 120 | PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) |
| 121 | PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) |
| 122 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 123 | /* Top PCI device */ |
| 124 | Device (PCI0) |
| 125 | { |
| 126 | Name (_HID, EisaId ("PNP0A03")) |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 127 | Name (_UID, 0x00) |
| 128 | Name (_BBN, 0x00) |
| 129 | |
| 130 | /* PCI Routing Table */ |
| 131 | Name (_PRT, Package () { |
| 132 | Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, |
| 133 | Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, |
| 134 | Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, |
| 135 | Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, |
| 136 | |
| 137 | Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, |
| 138 | Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, |
| 139 | Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, |
| 140 | Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, |
| 141 | |
| 142 | Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, |
| 143 | Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, |
| 144 | Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, |
| 145 | Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, |
| 146 | |
| 147 | Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, |
| 148 | Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, |
| 149 | Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, |
| 150 | Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, |
| 151 | |
| 152 | Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, |
| 153 | Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, |
| 154 | Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, |
| 155 | Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, |
| 156 | |
| 157 | Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, |
| 158 | Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, |
| 159 | Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, |
| 160 | Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, |
| 161 | |
| 162 | }) |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 163 | #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 164 | |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 165 | /* Begin southbridge block */ |
| 166 | Device (PX40) |
| 167 | { |
| 168 | Name(_ADR, 0x00040000) |
| 169 | OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) |
| 170 | Field (PIRQ, ByteAcc, NoLock, Preserve) |
| 171 | { |
| 172 | PIRA, 8, |
| 173 | PIRB, 8, |
| 174 | PIRC, 8, |
| 175 | PIRD, 8 |
| 176 | } |
| 177 | |
| 178 | /* PNP Motherboard Resources */ |
| 179 | Device (SYSR) |
| 180 | { |
| 181 | Name (_HID, EisaId ("PNP0C02")) |
| 182 | Method (_CRS, 0, NotSerialized) |
| 183 | { |
| 184 | Name (BUF1, ResourceTemplate () |
| 185 | { |
| 186 | /* PM register ports */ |
| 187 | IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) |
| 188 | /* SMBus register ports */ |
| 189 | IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) |
| 190 | /* PIIX4E ports */ |
| 191 | /* Aliased DMA ports */ |
| 192 | IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) |
| 193 | /* Aliased PIC ports */ |
| 194 | IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) |
| 195 | /* Aliased timer ports */ |
| 196 | IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) |
| 197 | IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) |
| 198 | IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) |
| 199 | IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) |
| 200 | IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) |
| 201 | IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) |
| 202 | IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) |
| 203 | IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) |
| 204 | IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) |
| 205 | IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) |
| 206 | }) |
| 207 | CreateWordField (BUF1, _Y06._MIN, PMLO) |
| 208 | CreateWordField (BUF1, _Y06._MAX, PMRL) |
| 209 | CreateWordField (BUF1, _Y07._MIN, SBLO) |
| 210 | CreateWordField (BUF1, _Y07._MAX, SBRL) |
| 211 | |
| 212 | And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) |
| 213 | And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) |
| 214 | Store (PMLO, PMRL) |
| 215 | Store (SBLO, SBRL) |
| 216 | Return (BUF1) |
| 217 | } |
| 218 | } |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 219 | #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 220 | } |
| 221 | Device (PX43) |
| 222 | { |
| 223 | Name (_ADR, 0x00040003) // _ADR: Address |
| 224 | OperationRegion (IPMU, PCI_Config, PMBA, 0x02) |
| 225 | Field (IPMU, ByteAcc, NoLock, Preserve) |
| 226 | { |
| 227 | PM00, 16 |
| 228 | } |
| 229 | |
| 230 | OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) |
| 231 | Field (ISMB, ByteAcc, NoLock, Preserve) |
| 232 | { |
| 233 | SB00, 16 |
| 234 | } |
| 235 | } |
| 236 | |
Elyes HAOUAS | 2c5652d | 2018-10-14 10:51:13 +0200 | [diff] [blame] | 237 | #include <superio/winbond/w83977tf/acpi/superio.asl> |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 238 | } |
Keith Hui | 819005f | 2017-11-14 23:31:20 -0500 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | /* ACPI Message */ |
| 242 | Scope (\_SI) |
| 243 | { |
| 244 | Method (_MSG, 1, NotSerialized) |
| 245 | { |
| 246 | If (LEqual (Arg0, Zero)) |
| 247 | { |
| 248 | Store (One, MSG0) |
| 249 | } |
| 250 | Else |
| 251 | { |
| 252 | Store (Zero, MSG0) |
| 253 | } |
| 254 | } |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 255 | } |
| 256 | } |