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review.coreboot.org / coreboot / 3f882fafa069ce3c7cb39bdc80c73ade3f0daa46 / . / Documentation / Intel / fsp1_1.html
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Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>FSP 1.1</title>
5 </head>
6 <body>
7
Jonathan Neuschäfer7719d502018-04-15 20:33:50 +0200[diff] [blame]8<h1>FSP 1.1</h1>
9
10<h2>x86 FSP 1.1 Integration</h2>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]11<p>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]12 Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC)
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 and board support. The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]14 <a target="_blank" href="development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]15 The development steps for FSP are listed below:
16</p>
17<ol>
18 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]19 <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]20 <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]21</ol>
22
23<p>
24 FSP Documentation:
25</p>
26<ul>
27 <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
28</ul>
29
30<hr>
Jonathan Neuschäfer7719d502018-04-15 20:33:50 +0200[diff] [blame]31<h2><a name="RequiredFiles">Required Files</a></h2>
32<h3><a name="corebootRequiredFiles">coreboot Required Files</a></h3>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]33<ol>
34 <li>Create the following directories if they do not already exist:
35 <ul>
36 <li>src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;</li>
37 <li>3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;</li>
38 </ul>
39 </li>
40 <li>
41 The following files may need to be copied from the FSP build or release into the
42 directories above if they are not present or are out of date:
43 <ul>
44 <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;/FspUpdVpd.h</li>
45 <li>FSP.bin: 3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;/fsp.bin</li>
46 </ul>
47 </li>
48</ol>
49
50
51<hr>
Jonathan Neuschäfer7719d502018-04-15 20:33:50 +0200[diff] [blame]52<h2><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h2>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]53<p>
54 Add the FSP binary to the coreboot flash image using the following command:
55</p>
56<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b &lt;base address&gt; -f fsp.bin</code></pre>
57<p>
58 This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
59 FSP code for TempRamInit may be executed in place.
60</p>
61
62
63<hr>
Jonathan Neuschäfer7719d502018-04-15 20:33:50 +0200[diff] [blame]64<h2><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h2>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]65<p>
66 Set the following Kconfig values:
67</p>
68<ul>
69 <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
70 <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
71 <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
72 <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
73</ul>
74
75
76<hr>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]77<p>Modified: 17 May 2016</p>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]78 </body>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]79</html>