Andrey Petrov | 3f85edb | 2019-08-01 14:18:06 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2019 Facebook, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <cbmem.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/dram/ddr4.h> |
| 20 | #include <string.h> |
| 21 | #include <memory_info.h> |
| 22 | #include <smbios.h> |
| 23 | #include <types.h> |
| 24 | |
| 25 | typedef enum { |
| 26 | BLOCK_0, /* Base Configuration and DRAM Parameters */ |
| 27 | BLOCK_1, |
| 28 | BLOCK_1_L, /* Standard Module Parameters */ |
| 29 | BLOCK_1_H, /* Hybrid Module Parameters */ |
| 30 | BLOCK_2, |
| 31 | BLOCK_2_L, /* Hybrid Module Extended Function Parameters */ |
| 32 | BLOCK_2_H, /* Manufacturing Information */ |
| 33 | BLOCK_3 /* End user programmable */ |
| 34 | } spd_block_type; |
| 35 | |
| 36 | typedef struct { |
| 37 | spd_block_type type; |
| 38 | uint16_t start; /* starting offset from beginning of the spd */ |
| 39 | uint16_t len; /* size of the block */ |
| 40 | uint16_t crc_start; /* offset from start of crc bytes, 0 if none */ |
| 41 | } spd_block; |
| 42 | |
| 43 | /* 'SPD contents architecture' as per datasheet */ |
| 44 | const spd_block spd_blocks[] = { |
| 45 | {.type = BLOCK_0, 0, 128, 126}, {.type = BLOCK_1, 128, 128, 126}, |
| 46 | {.type = BLOCK_1_L, 128, 64, 0}, {.type = BLOCK_1_H, 192, 64, 0}, |
| 47 | {.type = BLOCK_2_L, 256, 64, 62}, {.type = BLOCK_2_H, 320, 64, 0}, |
| 48 | {.type = BLOCK_3, 384, 128, 0} }; |
| 49 | |
| 50 | static bool verify_block(const spd_block *block, spd_raw_data spd) |
| 51 | { |
| 52 | uint16_t crc, spd_crc; |
| 53 | |
| 54 | spd_crc = (spd[block->start + block->crc_start + 1] << 8) |
| 55 | | spd[block->start + block->crc_start]; |
| 56 | crc = ddr_crc16(&spd[block->start], block->len - 2); |
| 57 | |
| 58 | return spd_crc == crc; |
| 59 | } |
| 60 | |
| 61 | /* Check if given block is 'reserved' for a given module type */ |
| 62 | static bool block_exists(spd_block_type type, u8 dimm_type) |
| 63 | { |
| 64 | bool is_hybrid; |
| 65 | |
| 66 | switch (type) { |
| 67 | case BLOCK_0: /* fall-through */ |
| 68 | case BLOCK_1: /* fall-through */ |
| 69 | case BLOCK_1_L: /* fall-through */ |
| 70 | case BLOCK_1_H: /* fall-through */ |
| 71 | case BLOCK_2_H: /* fall-through */ |
| 72 | case BLOCK_3: /* fall-through */ |
| 73 | return true; |
| 74 | case BLOCK_2_L: |
| 75 | is_hybrid = (dimm_type >> 4) & ((1 << 3) - 1); |
| 76 | if (is_hybrid) |
| 77 | return true; |
| 78 | return false; |
| 79 | default: /* fall-through */ |
| 80 | return false; |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /** |
| 86 | * \brief Decode the raw SPD data |
| 87 | * |
| 88 | * Decodes a raw SPD data from a DDR4 DIMM, and organizes it into a |
| 89 | * @ref dimm_attr structure. The SPD data must first be read in a contiguous |
| 90 | * array, and passed to this function. |
| 91 | * |
| 92 | * @param dimm pointer to @ref dimm_attr structure where the decoded data is to |
| 93 | * be stored |
| 94 | * @param spd array of raw data previously read from the SPD. |
| 95 | * |
| 96 | * @return @ref spd_status enumerator |
| 97 | * SPD_STATUS_OK -- decoding was successful |
| 98 | * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD |
| 99 | * SPD_STATUS_CRC_ERROR -- checksum mismatch |
| 100 | */ |
| 101 | int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) |
| 102 | { |
| 103 | u8 reg8; |
| 104 | u8 bus_width, sdram_width; |
| 105 | u16 cap_per_die_mbit; |
| 106 | u16 spd_bytes_total, spd_bytes_used; |
| 107 | const uint16_t spd_bytes_used_table[] = {0, 128, 256, 384, 512}; |
| 108 | |
| 109 | /* Make sure that the SPD dump is indeed from a DDR4 module */ |
| 110 | if (spd[2] != SPD_MEMORY_TYPE_DDR4_SDRAM) { |
| 111 | printk(BIOS_ERR, "Not a DDR4 SPD!\n"); |
| 112 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 113 | return SPD_STATUS_INVALID; |
| 114 | } |
| 115 | |
| 116 | spd_bytes_total = (spd[0] >> 4) & ((1 << 3) - 1); |
| 117 | spd_bytes_used = spd[0] & ((1 << 4) - 1); |
| 118 | |
| 119 | if (!spd_bytes_total || !spd_bytes_used) { |
| 120 | printk(BIOS_ERR, "SPD failed basic sanity checks\n"); |
| 121 | return SPD_STATUS_INVALID; |
| 122 | } |
| 123 | |
| 124 | spd_bytes_total = 256 << (spd_bytes_total - 1); |
| 125 | spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; |
| 126 | |
| 127 | /* Verify CRC of blocks that have them, do not step over 'used' length */ |
| 128 | for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { |
| 129 | /* this block is not checksumed */ |
| 130 | if (spd_blocks[i].crc_start == 0) |
| 131 | continue; |
| 132 | /* we shouldn't have this block */ |
| 133 | if (spd_blocks[i].start + spd_blocks[i].len > spd_bytes_used) |
| 134 | continue; |
| 135 | /* check if block exists in the current schema */ |
| 136 | if (!block_exists(spd_blocks[i].type, spd[3])) |
| 137 | continue; |
| 138 | if (!verify_block(&spd_blocks[i], spd)) { |
| 139 | printk(BIOS_ERR, "CRC failed for block %d\n", i); |
| 140 | return SPD_STATUS_CRC_ERROR; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | dimm->dram_type = SPD_MEMORY_TYPE_DDR4_SDRAM; |
| 145 | dimm->dimm_type = spd[3] & ((1 << 4) - 1); |
| 146 | |
| 147 | reg8 = spd[13] & ((1 << 4) - 1); |
| 148 | dimm->bus_width = reg8; |
| 149 | bus_width = 8 << (reg8 & ((1 << 3) - 1)); |
| 150 | |
| 151 | reg8 = spd[12] & ((1 << 3) - 1); |
| 152 | dimm->sdram_width = reg8; |
| 153 | sdram_width = 4 << reg8; |
| 154 | |
| 155 | reg8 = spd[4] & ((1 << 4) - 1); |
| 156 | dimm->cap_per_die_mbit = reg8; |
| 157 | cap_per_die_mbit = (1 << reg8) * 256; |
| 158 | |
| 159 | reg8 = (spd[12] >> 3) & ((1 << 3) - 1); |
| 160 | dimm->ranks = reg8 + 1; |
| 161 | |
| 162 | if (!bus_width || !sdram_width) { |
| 163 | printk(BIOS_ERR, "SPD information is invalid"); |
| 164 | dimm->size_mb = 0; |
| 165 | return SPD_STATUS_INVALID; |
| 166 | } |
| 167 | |
| 168 | /* seems to be only one, in mV */ |
| 169 | dimm->vdd_voltage = 1200; |
| 170 | |
| 171 | /* calculate size */ |
| 172 | dimm->size_mb = cap_per_die_mbit / 8 * bus_width / sdram_width * dimm->ranks; |
| 173 | |
| 174 | /* make sure we have the manufacturing information block */ |
| 175 | if (spd_bytes_used > 320) { |
| 176 | dimm->manufacturer_id = (spd[351] << 8) | spd[350]; |
| 177 | memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN); |
| 178 | dimm->part_number[SPD_DDR4_PART_LEN] = 0; |
| 179 | memcpy(dimm->serial_number, &spd[325], sizeof(dimm->serial_number)); |
| 180 | } |
| 181 | return SPD_STATUS_OK; |
| 182 | } |
| 183 | |
| 184 | enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, |
| 185 | const dimm_attr *info) |
| 186 | { |
| 187 | struct memory_info *mem_info; |
| 188 | struct dimm_info *dimm; |
| 189 | |
| 190 | /* |
| 191 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 192 | * table 17 |
| 193 | */ |
| 194 | mem_info = cbmem_find(CBMEM_ID_MEMINFO); |
| 195 | if (!mem_info) { |
| 196 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 197 | |
| 198 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); |
| 199 | if (!mem_info) |
| 200 | return CB_ERR; |
| 201 | |
| 202 | memset(mem_info, 0, sizeof(*mem_info)); |
| 203 | } |
| 204 | |
| 205 | if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) { |
| 206 | printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__); |
| 207 | return CB_ERR; |
| 208 | } |
| 209 | |
| 210 | dimm = &mem_info->dimm[mem_info->dimm_cnt]; |
| 211 | if (info->size_mb) { |
| 212 | dimm->ddr_type = MEMORY_TYPE_DDR4; |
| 213 | dimm->ddr_frequency = selected_freq; |
| 214 | dimm->dimm_size = info->size_mb; |
| 215 | dimm->channel_num = channel; |
| 216 | dimm->rank_per_dimm = info->ranks; |
| 217 | dimm->dimm_num = slot; |
| 218 | memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); |
| 219 | dimm->mod_id = info->manufacturer_id; |
| 220 | |
| 221 | switch (info->dimm_type) { |
| 222 | case SPD_DIMM_TYPE_SO_DIMM: |
| 223 | dimm->mod_type = SPD_SODIMM; |
| 224 | break; |
| 225 | case SPD_DIMM_TYPE_72B_SO_RDIMM: |
| 226 | dimm->mod_type = SPD_72B_SO_RDIMM; |
| 227 | break; |
| 228 | case SPD_DIMM_TYPE_UDIMM: |
| 229 | dimm->mod_type = SPD_UDIMM; |
| 230 | break; |
| 231 | case SPD_DIMM_TYPE_RDIMM: |
| 232 | dimm->mod_type = SPD_RDIMM; |
| 233 | break; |
| 234 | default: |
| 235 | dimm->mod_type = SPD_UNDEFINED; |
| 236 | break; |
| 237 | } |
| 238 | |
| 239 | dimm->bus_width = info->bus_width; |
| 240 | memcpy(dimm->serial, info->serial_number, |
| 241 | MIN(sizeof(dimm->serial), sizeof(info->serial_number))); |
| 242 | |
| 243 | dimm->vdd_voltage = info->vdd_voltage; |
| 244 | mem_info->dimm_cnt++; |
| 245 | } |
| 246 | |
| 247 | return CB_SUCCESS; |
| 248 | } |