Andrey Petrov | a00e104 | 2017-06-05 13:22:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <cpu/x86/msr.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <soc/bootblock.h> |
| 24 | #include <soc/cpu.h> |
| 25 | #include <soc/pch.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <string.h> |
| 28 | |
| 29 | #define BIOS_SIGN_ID 0x8B |
| 30 | |
| 31 | static struct { |
| 32 | u32 cpuid; |
| 33 | const char *name; |
| 34 | } cpu_table[] = { |
| 35 | { CPUID_CANNONLAKE_A0, "Cannonlake A0" }, |
| 36 | { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, |
| 37 | { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, |
| 38 | }; |
| 39 | |
| 40 | static struct { |
| 41 | u16 mchid; |
| 42 | const char *name; |
| 43 | } mch_table[] = { |
| 44 | { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, |
| 45 | { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, |
| 46 | }; |
| 47 | |
| 48 | static struct { |
| 49 | u16 igdid; |
| 50 | const char *name; |
| 51 | } igd_table[] = { |
| 52 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" }, |
| 53 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" }, |
| 54 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" }, |
| 55 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" }, |
| 56 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" }, |
| 57 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" }, |
| 58 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, |
| 59 | { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, |
| 60 | }; |
| 61 | |
| 62 | static void report_cpu_info(void) |
| 63 | { |
| 64 | struct cpuid_result cpuidr; |
| 65 | u32 i, index; |
| 66 | char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ |
| 67 | int vt, txt, aes; |
| 68 | msr_t microcode_ver; |
| 69 | static const char * const mode[] = {"NOT ", ""}; |
| 70 | const char *cpu_type = "Unknown"; |
Martin Roth | 3f6421e | 2017-07-21 09:17:58 -0600 | [diff] [blame^] | 71 | u32 p[13]; |
Andrey Petrov | a00e104 | 2017-06-05 13:22:59 -0700 | [diff] [blame] | 72 | |
| 73 | index = 0x80000000; |
| 74 | cpuidr = cpuid(index); |
| 75 | if (cpuidr.eax < 0x80000004) { |
| 76 | strcpy(cpu_string, "Platform info not available"); |
| 77 | } else { |
Andrey Petrov | a00e104 | 2017-06-05 13:22:59 -0700 | [diff] [blame] | 78 | int j=0; |
| 79 | |
| 80 | for (i = 2; i <= 4; i++) { |
| 81 | cpuidr = cpuid(index + i); |
| 82 | p[j++] = cpuidr.eax; |
| 83 | p[j++] = cpuidr.ebx; |
| 84 | p[j++] = cpuidr.ecx; |
| 85 | p[j++] = cpuidr.edx; |
| 86 | } |
| 87 | p[12]=0; |
| 88 | cpu_name = (char *)p; |
| 89 | } |
| 90 | /* Skip leading spaces in CPU name string */ |
| 91 | while (cpu_name[0] == ' ') |
| 92 | cpu_name++; |
| 93 | |
| 94 | microcode_ver.lo = 0; |
| 95 | microcode_ver.hi = 0; |
| 96 | wrmsr(BIOS_SIGN_ID, microcode_ver); |
| 97 | cpuidr = cpuid(1); |
| 98 | microcode_ver = rdmsr(BIOS_SIGN_ID); |
| 99 | |
| 100 | /* Look for string to match the name */ |
| 101 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 102 | if (cpu_table[i].cpuid == cpuidr.eax) { |
| 103 | cpu_type = cpu_table[i].name; |
| 104 | break; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 109 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 110 | cpuidr.eax, cpu_type, microcode_ver.hi); |
| 111 | |
| 112 | aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; |
| 113 | txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; |
| 114 | vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; |
| 115 | printk(BIOS_DEBUG, |
| 116 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 117 | mode[aes], mode[txt], mode[vt]); |
| 118 | } |
| 119 | |
| 120 | static void report_mch_info(void) |
| 121 | { |
| 122 | int i; |
| 123 | u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); |
| 124 | u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); |
| 125 | const char *mch_type = "Unknown"; |
| 126 | |
| 127 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 128 | if (mch_table[i].mchid == mchid) { |
| 129 | mch_type = mch_table[i].name; |
| 130 | break; |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 135 | mchid, mch_revision, mch_type); |
| 136 | } |
| 137 | |
| 138 | static void report_igd_info(void) |
| 139 | { |
| 140 | int i; |
| 141 | u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); |
| 142 | const char *igd_type = "Unknown"; |
| 143 | |
| 144 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 145 | if (igd_table[i].igdid == igdid) { |
| 146 | igd_type = igd_table[i].name; |
| 147 | break; |
| 148 | } |
| 149 | } |
| 150 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 151 | igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); |
| 152 | } |
| 153 | |
| 154 | void report_platform_info(void) |
| 155 | { |
| 156 | report_cpu_info(); |
| 157 | report_mch_info(); |
| 158 | report_igd_info(); |
| 159 | } |