Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | # Auto-switch between X4 NVMe and X2 NVMe. |
| 3 | register "TetonGlacierMode" = "1" |
| 4 | |
| 5 | register "SerialIoDevMode" = "{ |
| 6 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
Matt Ziegelbaum | ba358a7 | 2021-10-11 23:44:44 -0400 | [diff] [blame] | 7 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 8 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 9 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
Matt Ziegelbaum | ba358a7 | 2021-10-11 23:44:44 -0400 | [diff] [blame] | 10 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 11 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 12 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
| 13 | [PchSerialIoIndexSPI1] = PchSerialIoPci, |
| 14 | [PchSerialIoIndexSPI2] = PchSerialIoDisabled, |
| 15 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 16 | [PchSerialIoIndexUART1] = PchSerialIoPci, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 17 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 18 | }" |
| 19 | |
| 20 | # USB configuration |
| 21 | register "usb2_ports[0]" = "{ |
| 22 | .enable = 1, |
| 23 | .ocpin = OC2, |
| 24 | .tx_bias = USB2_BIAS_0MV, |
| 25 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 26 | .pre_emp_bias = USB2_BIAS_11P25MV, |
| 27 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 28 | }" # Type-A Port 2 |
| 29 | register "usb2_ports[1]" = "{ |
| 30 | .enable = 1, |
| 31 | .ocpin = OC1, |
| 32 | .tx_bias = USB2_BIAS_0MV, |
| 33 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 34 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 35 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 36 | }" # Type-A Port 1 |
| 37 | register "usb2_ports[2]" = "{ |
| 38 | .enable = 1, |
| 39 | .ocpin = OC3, |
| 40 | .tx_bias = USB2_BIAS_0MV, |
| 41 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 42 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 43 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 44 | }" # Type-A Port 3 |
Kenneth Chan | 1d3cff3 | 2021-12-15 14:05:40 +0800 | [diff] [blame] | 45 | register "usb2_ports[3]" = "{ |
| 46 | .enable = 1, |
| 47 | .ocpin = OC_SKIP, |
| 48 | .tx_bias = USB2_BIAS_0MV, |
| 49 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 50 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 51 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 52 | }" # Type-C Port |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 53 | register "usb2_ports[4]" = "{ |
| 54 | .enable = 1, |
| 55 | .ocpin = OC_SKIP, |
| 56 | .tx_bias = USB2_BIAS_0MV, |
| 57 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 58 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 59 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 60 | }" # Type-A Port 4 |
| 61 | register "usb2_ports[5]" = "{ |
| 62 | .enable = 1, |
| 63 | .ocpin = OC0, |
| 64 | .tx_bias = USB2_BIAS_0MV, |
| 65 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 66 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 67 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 68 | }" # Type-A port 0 |
| 69 | register "usb2_ports[6]" = "USB2_PORT_EMPTY" |
| 70 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" |
| 71 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" |
| 72 | register "usb2_ports[9]" = "{ |
| 73 | .enable = 1, |
| 74 | .ocpin = OC_SKIP, |
| 75 | .tx_bias = USB2_BIAS_0MV, |
| 76 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 77 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 78 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 79 | }" # BT |
| 80 | |
| 81 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 |
| 82 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 |
| 83 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 |
| 84 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C |
| 85 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 |
| 86 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 |
| 87 | |
| 88 | # Bitmap for Wake Enable on USB attach/detach |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 89 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 90 | USB_PORT_WAKE_ENABLE(2) | |
| 91 | USB_PORT_WAKE_ENABLE(3) | |
| 92 | USB_PORT_WAKE_ENABLE(5) | |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 93 | USB_PORT_WAKE_ENABLE(6)" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 94 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 95 | USB_PORT_WAKE_ENABLE(2) | |
| 96 | USB_PORT_WAKE_ENABLE(3) | |
| 97 | USB_PORT_WAKE_ENABLE(5) | |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 98 | USB_PORT_WAKE_ENABLE(6)" |
| 99 | |
| 100 | # Enable eMMC HS400 |
| 101 | register "ScsEmmcHs400Enabled" = "1" |
| 102 | |
| 103 | # EMMC Tx CMD Delay |
| 104 | # Refer to EDS-Vol2-14.3.7. |
| 105 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 106 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 107 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 108 | |
| 109 | # EMMC TX DATA Delay 1 |
| 110 | # Refer to EDS-Vol2-14.3.8. |
| 111 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 112 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 113 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" |
| 114 | |
| 115 | # EMMC TX DATA Delay 2 |
| 116 | # Refer to EDS-Vol2-14.3.9. |
| 117 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 118 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 119 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 120 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 121 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" |
| 122 | |
| 123 | # EMMC RX CMD/DATA Delay 1 |
| 124 | # Refer to EDS-Vol2-14.3.10. |
| 125 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 126 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 127 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 128 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 129 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" |
| 130 | |
| 131 | # EMMC RX CMD/DATA Delay 2 |
| 132 | # Refer to EDS-Vol2-14.3.12. |
| 133 | # [17:16] stands for Rx Clock before Output Buffer, |
| 134 | # 00: Rx clock after output buffer, |
| 135 | # 01: Rx clock before output buffer, |
| 136 | # 10: Automatic selection based on working mode. |
| 137 | # 11: Reserved |
| 138 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 139 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 140 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" |
| 141 | |
| 142 | # EMMC Rx Strobe Delay |
| 143 | # Refer to EDS-Vol2-14.3.11. |
| 144 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 145 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 146 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" |
| 147 | |
| 148 | # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. |
| 149 | register "PchHdaAudioLinkSsp1" = "0" |
| 150 | register "PchHdaAudioLinkDmic0" = "0" |
| 151 | |
| 152 | # Intel Common SoC Config |
| 153 | #+-------------------+---------------------------+ |
| 154 | #| Field | Value | |
| 155 | #+-------------------+---------------------------+ |
| 156 | #| GSPI0 | cr50 TPM. Early init is | |
| 157 | #| | required to set up a BAR | |
| 158 | #| | for TPM communication | |
| 159 | #| | before memory is up | |
Matt Ziegelbaum | ba358a7 | 2021-10-11 23:44:44 -0400 | [diff] [blame] | 160 | #| I2C1 | USI (Touch screen) | |
| 161 | #| I2C2 | SCALER | |
| 162 | #| I2C3 | TPU | |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 163 | #+-------------------+---------------------------+ |
| 164 | register "common_soc_config" = "{ |
| 165 | .gspi[0] = { |
| 166 | .speed_mhz = 1, |
| 167 | .early_init = 1, |
| 168 | }, |
Matt Ziegelbaum | ba358a7 | 2021-10-11 23:44:44 -0400 | [diff] [blame] | 169 | .i2c[1] = { |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 170 | .speed = I2C_SPEED_FAST, |
Matt Ziegelbaum | ba358a7 | 2021-10-11 23:44:44 -0400 | [diff] [blame] | 171 | .rise_time_ns = 60, |
| 172 | .fall_time_ns = 60, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 173 | }, |
| 174 | .i2c[2] = { |
| 175 | .speed = I2C_SPEED_FAST, |
| 176 | .rise_time_ns = 60, |
| 177 | .fall_time_ns = 60, |
| 178 | }, |
| 179 | .i2c[3] = { |
| 180 | .speed = I2C_SPEED_FAST, |
| 181 | .rise_time_ns = 60, |
| 182 | .fall_time_ns = 60, |
| 183 | }, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 184 | }" |
| 185 | |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 186 | # PCIe root port 7 for LAN |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 187 | register "PcieRpEnable[6]" = "1" |
| 188 | register "PcieRpLtrEnable[6]" = "1" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 189 | # Uses CLK SRC 0 |
| 190 | register "PcieClkSrcUsage[0]" = "6" |
| 191 | register "PcieClkSrcClkReq[0]" = "0" |
| 192 | |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 193 | # PCIe root port 8 for WLAN |
| 194 | register "PcieRpEnable[7]" = "1" |
| 195 | register "PcieRpLtrEnable[7]" = "1" |
| 196 | # Uses CLK SRC 3 |
| 197 | register "PcieClkSrcUsage[3]" = "7" |
| 198 | register "PcieClkSrcClkReq[3]" = "3" |
| 199 | |
| 200 | # PCIe root port 9 for SSD (PCIe Lanes 9-12) |
| 201 | register "PcieRpEnable[8]" = "1" |
| 202 | register "PcieRpLtrEnable[8]" = "1" |
| 203 | # RP 9 uses CLK SRC 1 |
| 204 | register "PcieClkSrcUsage[1]" = "8" |
| 205 | register "PcieClkSrcClkReq[1]" = "1" |
| 206 | |
| 207 | # PCIe root port 10-12 disabled |
| 208 | register "PcieRpEnable[9]" = "0" |
| 209 | register "PcieRpEnable[10]" = "0" |
| 210 | register "PcieRpEnable[11]" = "0" |
| 211 | |
| 212 | # PCIe root port 13 TPU0 |
| 213 | register "PcieRpEnable[12]" = "1" |
| 214 | register "PcieRpLtrEnable[12]" = "1" |
| 215 | # RP 13 uses CLK SRC 2 |
| 216 | register "PcieClkSrcUsage[2]" = "12" |
| 217 | register "PcieClkSrcClkReq[2]" = "2" |
| 218 | |
| 219 | # PCIe root port 14 TPU1 |
| 220 | register "PcieRpEnable[13]" = "1" |
| 221 | register "PcieRpLtrEnable[13]" = "1" |
| 222 | # RP 14 uses CLK SRC 4 |
| 223 | register "PcieClkSrcUsage[4]" = "13" |
| 224 | register "PcieClkSrcClkReq[4]" = "4" |
| 225 | |
| 226 | register "PcieRpEnable[14]" = "0" |
| 227 | register "PcieRpEnable[15]" = "0" |
| 228 | |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 229 | # GPIO for SD card detect |
| 230 | register "sdcard_cd_gpio" = "vSD3_CD_B" |
| 231 | |
| 232 | # SATA port 1 Gen3 Strength |
| 233 | # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB |
| 234 | register "sata_port[1].TxGen3DeEmphEnable" = "1" |
| 235 | register "sata_port[1].TxGen3DeEmph" = "0x20" |
| 236 | |
| 237 | device domain 0 on |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 238 | device ref dptf on |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 239 | chip drivers/intel/dptf |
| 240 | ## Active Policy |
| 241 | register "policies.active[0]" = "{.target=DPTF_CPU, |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 242 | .thresholds={TEMP_PCT(94, 0),}}" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 243 | register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, |
Kenneth Chan | 9b9fe92 | 2022-01-06 16:42:48 +0800 | [diff] [blame] | 244 | .thresholds={TEMP_PCT(82, 80), |
Kenneth Chan | bde3c56 | 2021-08-05 11:32:15 +0800 | [diff] [blame] | 245 | TEMP_PCT(80, 70), |
Kenneth Chan | 9b9fe92 | 2022-01-06 16:42:48 +0800 | [diff] [blame] | 246 | TEMP_PCT(78, 60), |
| 247 | TEMP_PCT(75, 50), |
| 248 | TEMP_PCT(73, 40), |
| 249 | TEMP_PCT(35, 30),}}" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 250 | |
| 251 | ## Passive Policy |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 252 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" |
Kenneth Chan | bde3c56 | 2021-08-05 11:32:15 +0800 | [diff] [blame] | 253 | register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000)" |
| 254 | register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000)" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 255 | |
| 256 | ## Critical Policy |
| 257 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" |
Kenneth Chan | bde3c56 | 2021-08-05 11:32:15 +0800 | [diff] [blame] | 258 | register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" |
| 259 | register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN)" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 260 | |
| 261 | ## Power Limits Control |
| 262 | # PL1 is fixed at 15W, avg over 28-32s interval |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 263 | # 51-51W PL2 in 1000mW increments, avg over 28-32s interval |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 264 | register "controls.power_limits.pl1" = "{ |
| 265 | .min_power = 15000, |
| 266 | .max_power = 15000, |
| 267 | .time_window_min = 28 * MSECS_PER_SEC, |
| 268 | .time_window_max = 32 * MSECS_PER_SEC, |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 269 | .granularity = 125,}" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 270 | register "controls.power_limits.pl2" = "{ |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 271 | .min_power = 51000, |
| 272 | .max_power = 51000, |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 273 | .time_window_min = 28 * MSECS_PER_SEC, |
| 274 | .time_window_max = 32 * MSECS_PER_SEC, |
| 275 | .granularity = 1000,}" |
| 276 | |
| 277 | ## Charger Performance Control (Control, mA) |
| 278 | register "controls.charger_perf[0]" = "{ 255, 1700 }" |
| 279 | register "controls.charger_perf[1]" = "{ 24, 1500 }" |
| 280 | register "controls.charger_perf[2]" = "{ 16, 1000 }" |
| 281 | register "controls.charger_perf[3]" = "{ 8, 500 }" |
| 282 | |
| 283 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 284 | register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" |
| 285 | register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" |
| 286 | register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" |
| 287 | register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" |
| 288 | register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" |
| 289 | register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" |
| 290 | register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" |
| 291 | register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" |
| 292 | register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" |
| 293 | register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" |
| 294 | |
| 295 | # Fan options |
| 296 | register "options.fan.fine_grained_control" = "1" |
| 297 | register "options.fan.step_size" = "2" |
| 298 | |
| 299 | device generic 0 on end |
| 300 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 301 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 302 | device ref xhci on |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 303 | chip drivers/usb/acpi |
| 304 | device usb 0.0 on |
| 305 | chip drivers/usb/acpi |
| 306 | register "desc" = ""USB2 Type-A Front Left"" |
| 307 | register "type" = "UPC_TYPE_A" |
| 308 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 309 | device usb 2.0 on end |
| 310 | end |
| 311 | chip drivers/usb/acpi |
| 312 | register "desc" = ""USB2 Type-C Port Rear"" |
| 313 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 314 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 315 | device usb 2.1 on end |
| 316 | end |
| 317 | chip drivers/usb/acpi |
| 318 | register "desc" = ""USB2 Type-A Front Right"" |
| 319 | register "type" = "UPC_TYPE_A" |
| 320 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 321 | device usb 2.2 on end |
| 322 | end |
| 323 | chip drivers/usb/acpi |
| 324 | register "desc" = ""USB2 Type-A Rear Right"" |
| 325 | register "type" = "UPC_TYPE_A" |
| 326 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 327 | device usb 2.3 on end |
| 328 | end |
| 329 | chip drivers/usb/acpi |
| 330 | register "desc" = ""USB2 Type-A Rear Middle"" |
| 331 | register "type" = "UPC_TYPE_A" |
| 332 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 333 | device usb 2.4 on end |
| 334 | end |
| 335 | chip drivers/usb/acpi |
| 336 | register "desc" = ""USB2 Type-A Rear Left"" |
| 337 | register "type" = "UPC_TYPE_A" |
| 338 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 339 | device usb 2.5 on end |
| 340 | end |
| 341 | chip drivers/usb/acpi |
| 342 | device usb 2.6 off end |
| 343 | end |
| 344 | chip drivers/usb/acpi |
| 345 | register "desc" = ""USB3 Type-A Front Left"" |
| 346 | register "type" = "UPC_TYPE_USB3_A" |
| 347 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 348 | device usb 3.0 on end |
| 349 | end |
| 350 | chip drivers/usb/acpi |
| 351 | register "desc" = ""USB3 Type-A Front Right"" |
| 352 | register "type" = "UPC_TYPE_USB3_A" |
| 353 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 354 | device usb 3.1 on end |
| 355 | end |
| 356 | chip drivers/usb/acpi |
| 357 | register "desc" = ""USB3 Type-A Rear Right"" |
| 358 | register "type" = "UPC_TYPE_USB3_A" |
| 359 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 360 | device usb 3.2 on end |
| 361 | end |
| 362 | chip drivers/usb/acpi |
| 363 | register "desc" = ""USB3 Type-C Rear"" |
| 364 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 365 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 366 | device usb 3.3 on end |
| 367 | end |
| 368 | chip drivers/usb/acpi |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 369 | # USB3 Port 5 is not populated |
| 370 | device usb 3.4 off end |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 371 | end |
| 372 | chip drivers/usb/acpi |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 373 | register "desc" = ""USB3 M.2 HDMI-to-USB"" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 374 | register "type" = "UPC_TYPE_USB3_A" |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 375 | register "group" = "ACPI_PLD_GROUP(2, 0)" |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 376 | device usb 3.5 on end |
| 377 | end |
| 378 | end |
| 379 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 380 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 381 | device ref i2c1 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 382 | # USI (Touch screen) |
Rehan Ghori | 3fe7653 | 2022-03-02 20:06:59 -0500 | [diff] [blame] | 383 | chip drivers/i2c/hid |
| 384 | register "generic.hid" = ""ILTK0001"" |
| 385 | register "generic.desc" = ""ILITEK Touchscreen"" |
| 386 | register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" |
| 387 | register "generic.probed" = "1" |
| 388 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" |
| 389 | register "generic.reset_delay_ms" = "600" |
| 390 | register "generic.wake" = "GPE0_DW2_16" |
| 391 | register "generic.has_power_resource" = "1" |
Rehan Ghori | 3fe7653 | 2022-03-02 20:06:59 -0500 | [diff] [blame] | 392 | register "hid_desc_reg_offset" = "0x01" |
| 393 | device i2c 41 on end |
| 394 | end |
| 395 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 396 | device ref i2c2 on end # SCALER |
| 397 | device ref i2c3 on end # TPU |
| 398 | device ref emmc on end |
| 399 | device ref pcie_rp7 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 400 | # RTL8111H Ethernet NIC |
| 401 | chip drivers/net |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 402 | register "customized_leds" = "0x05af" |
| 403 | register "wake" = "GPE0_DW1_07" # GPP_C7 |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 404 | register "device_index" = "0" |
Alexis Savery | 8ba64cd | 2023-08-30 20:11:34 +0000 | [diff] [blame] | 405 | register "enable_aspm_l1_2" = "1" |
Matt DeVillier | f03b8fc | 2023-11-19 16:12:56 -0600 | [diff] [blame] | 406 | device pci 00.0 on end |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 407 | end |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 408 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 409 | device ref pcie_rp8 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 410 | # WLAN |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 411 | register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot |
| 412 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 413 | device ref pcie_rp9 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 414 | # SSD |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 415 | register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot |
| 416 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 417 | device ref pcie_rp13 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 418 | # TPU0 |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 419 | register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot |
| 420 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 421 | device ref pcie_rp14 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 422 | # TPU1 |
Jeff Chase | d9b714d | 2021-06-28 17:53:01 -0400 | [diff] [blame] | 423 | register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot |
| 424 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame^] | 425 | device ref pcie_rp15 on end # non-root |
| 426 | device ref pcie_rp16 on end # non-root |
| 427 | device ref uart1 on end |
Jeff Chase | 444c24a | 2021-06-03 16:43:20 -0400 | [diff] [blame] | 428 | end |
| 429 | |
| 430 | # VR Settings Configuration for 4 Domains |
| 431 | #+----------------+-------+-------+-------+-------+ |
| 432 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 433 | #+----------------+-------+-------+-------+-------+ |
| 434 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 435 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 436 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 437 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 438 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 439 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 440 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 441 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 442 | #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 443 | #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 444 | #+----------------+-------+-------+-------+-------+ |
| 445 | #Note: IccMax settings are moved to SoC code |
| 446 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 447 | .vr_config_enable = 1, |
| 448 | .psi1threshold = VR_CFG_AMP(20), |
| 449 | .psi2threshold = VR_CFG_AMP(5), |
| 450 | .psi3threshold = VR_CFG_AMP(1), |
| 451 | .psi3enable = 1, |
| 452 | .psi4enable = 1, |
| 453 | .imon_slope = 0x0, |
| 454 | .imon_offset = 0x0, |
| 455 | .icc_max = 0, |
| 456 | .voltage_limit = 1520, |
| 457 | .ac_loadline = 1004, |
| 458 | .dc_loadline = 1004, |
| 459 | }" |
| 460 | |
| 461 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 462 | .vr_config_enable = 1, |
| 463 | .psi1threshold = VR_CFG_AMP(20), |
| 464 | .psi2threshold = VR_CFG_AMP(5), |
| 465 | .psi3threshold = VR_CFG_AMP(1), |
| 466 | .psi3enable = 1, |
| 467 | .psi4enable = 1, |
| 468 | .imon_slope = 0x0, |
| 469 | .imon_offset = 0x0, |
| 470 | .icc_max = 0, |
| 471 | .voltage_limit = 1520, |
| 472 | .ac_loadline = 181, |
| 473 | .dc_loadline = 181, |
| 474 | }" |
| 475 | |
| 476 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 477 | .vr_config_enable = 1, |
| 478 | .psi1threshold = VR_CFG_AMP(20), |
| 479 | .psi2threshold = VR_CFG_AMP(5), |
| 480 | .psi3threshold = VR_CFG_AMP(1), |
| 481 | .psi3enable = 1, |
| 482 | .psi4enable = 1, |
| 483 | .imon_slope = 0x0, |
| 484 | .imon_offset = 0x0, |
| 485 | .icc_max = 0, |
| 486 | .voltage_limit = 1520, |
| 487 | .ac_loadline = 319, |
| 488 | .dc_loadline = 319, |
| 489 | }" |
| 490 | |
| 491 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 492 | .vr_config_enable = 1, |
| 493 | .psi1threshold = VR_CFG_AMP(20), |
| 494 | .psi2threshold = VR_CFG_AMP(5), |
| 495 | .psi3threshold = VR_CFG_AMP(1), |
| 496 | .psi3enable = 1, |
| 497 | .psi4enable = 1, |
| 498 | .imon_slope = 0x0, |
| 499 | .imon_offset = 0x0, |
| 500 | .icc_max = 0, |
| 501 | .voltage_limit = 1520, |
| 502 | .ac_loadline = 319, |
| 503 | .dc_loadline = 319, |
| 504 | }" |
| 505 | |
| 506 | end |