Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mtspd3.h |
| 6 | * |
| 7 | * Technology SPD support for DDR3 |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Tech/DDR3) |
| 12 | * @e \$Revision: 85961 $ @e \$Date: 2013-01-14 19:58:20 -0600 (Mon, 14 Jan 2013) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | #ifndef _MTSPD3_H_ |
| 46 | #define _MTSPD3_H_ |
| 47 | |
| 48 | /*---------------------------------------------------------------------------- |
| 49 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | /*----------------------------------------------------------------------------- |
| 55 | * DEFINITIONS AND MACROS |
| 56 | * |
| 57 | *----------------------------------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | /*=============================================================================== |
| 61 | * Jedec DDR III |
| 62 | *=============================================================================== |
| 63 | */ |
| 64 | #define SPD_BYTE_USED 0 |
| 65 | #define SPD_TYPE 2 /* SPD byte read location */ |
| 66 | #define JED_DDR_SDRAM 7 /* Jedec defined bit field */ |
| 67 | #define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ |
| 68 | #define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ |
| 69 | |
| 70 | #define SPD_DIMM_TYPE 3 |
| 71 | #define SPD_ATTRIB 21 |
| 72 | #define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ |
| 73 | #define JED_RDIMM 1 |
| 74 | #define JED_MINIRDIMM 5 |
| 75 | #define JED_UDIMM 2 |
| 76 | #define JED_SODIMM 3 |
| 77 | #define JED_LRDIMM 0xB |
| 78 | #define JED_72B_SOUDIMM 8 |
| 79 | #define JED_UNDEFINED 0 /* Undefined value */ |
| 80 | |
| 81 | #define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ |
| 82 | #define SPD_DENSITY 4 /* bit 3:0 */ |
| 83 | #define SPD_ROW_SZ 5 /* bit 5:3 */ |
| 84 | #define SPD_COL_SZ 5 /* bit 2:0 */ |
| 85 | #define SPD_RANKS 7 /* bit 5:3 */ |
| 86 | #define SPD_DEV_WIDTH 7 /* bit 2:0 */ |
| 87 | #define SPD_ECCBITS 8 /* bit 4:3 */ |
| 88 | #define JED_ECC 8 |
| 89 | #define SPD_RAWCARD 62 /* bit 2:0 */ |
| 90 | #define SPD_ADDRMAP 63 /* bit 0 */ |
| 91 | |
| 92 | #define SPD_CTLWRD03 70 /* bit 7:4 */ |
| 93 | #define SPD_CTLWRD04 71 /* bit 3:0 */ |
| 94 | #define SPD_CTLWRD05 71 /* bit 7:4 */ |
| 95 | |
| 96 | #define SPD_FTB 9 |
| 97 | |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame^] | 98 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) |
| 99 | |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 100 | #define SPD_DIVIDENT 10 |
| 101 | #define SPD_DIVISOR 11 |
| 102 | |
| 103 | #define SPD_TCK 12 |
| 104 | #define SPD_CASLO 14 |
| 105 | #define SPD_CASHI 15 |
| 106 | #define SPD_TAA 16 |
| 107 | |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 108 | #define SPD_TWR 17 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame^] | 109 | #define SPD_TRCD 18 |
| 110 | #define SPD_TRRD 19 |
| 111 | #define SPD_TRP 20 |
| 112 | #define SPD_UPPER_TRC 21 /* bits 7:4 */ |
| 113 | #define SPD_UPPER_TRAS 21 /* bits 3:0 */ |
| 114 | #define SPD_TRAS 22 |
| 115 | #define SPD_TRC 23 |
| 116 | |
| 117 | #define SPD_TRFC_LO 24 |
| 118 | #define SPD_TRFC_HI 25 |
| 119 | |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 120 | #define SPD_TWTR 26 |
| 121 | #define SPD_TRTP 27 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame^] | 122 | #define SPD_UPPER_TFAW 28 /* bits 3:0 */ |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 123 | #define SPD_TFAW 29 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame^] | 124 | |
| 125 | #endif |
| 126 | |
| 127 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) |
| 128 | |
| 129 | #define SPD_DIVIDENT 180 |
| 130 | #define SPD_DIVISOR 181 |
| 131 | |
| 132 | #define SPD_TCK 186 |
| 133 | #define SPD_CASLO 188 |
| 134 | #define SPD_CASHI 189 |
| 135 | #define SPD_TAA 187 |
| 136 | |
| 137 | #define SPD_TWR 193 |
| 138 | #define SPD_TRCD 192 |
| 139 | #define SPD_TRRD 202 |
| 140 | #define SPD_TRP 191 |
| 141 | #define SPD_UPPER_TRC 194 /* bits 7:4 */ |
| 142 | #define SPD_UPPER_TRAS 194 /* bits 3:0 */ |
| 143 | #define SPD_TRAS 195 |
| 144 | #define SPD_TRC 196 |
| 145 | |
| 146 | #define SPD_TRFC_LO 199 |
| 147 | #define SPD_TRFC_HI 200 |
| 148 | |
| 149 | #define SPD_TWTR 205 |
| 150 | #define SPD_TRTP 201 |
| 151 | #define SPD_UPPER_TFAW 203 /* bits 3:0 */ |
| 152 | #define SPD_TFAW 204 |
| 153 | |
| 154 | #endif |
| 155 | |
| 156 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) |
| 157 | |
| 158 | #define SPD_DIVIDENT 182 |
| 159 | #define SPD_DIVISOR 183 |
| 160 | |
| 161 | #define SPD_TCK 221 |
| 162 | #define SPD_CASLO 223 |
| 163 | #define SPD_CASHI 224 |
| 164 | #define SPD_TAA 222 |
| 165 | |
| 166 | #define SPD_TWR 228 |
| 167 | #define SPD_TRCD 227 |
| 168 | #define SPD_TRRD 237 |
| 169 | #define SPD_TRP 226 |
| 170 | #define SPD_UPPER_TRC 229 /* bits 7:4 */ |
| 171 | #define SPD_UPPER_TRAS 229 /* bits 3:0 */ |
| 172 | #define SPD_TRAS 230 |
| 173 | #define SPD_TRC 231 |
| 174 | |
| 175 | #define SPD_TRFC_LO 234 |
| 176 | #define SPD_TRFC_HI 235 |
| 177 | |
| 178 | #define SPD_TWTR 240 |
| 179 | #define SPD_TRTP 236 |
| 180 | #define SPD_UPPER_TFAW 238 /* bits 3:0 */ |
| 181 | #define SPD_TFAW 239 |
| 182 | |
| 183 | #endif |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 184 | |
| 185 | #define SPD_TCK_FTB 34 |
| 186 | #define SPD_TAA_FTB 35 |
| 187 | #define SPD_TRCD_FTB 36 |
| 188 | #define SPD_TRP_FTB 37 |
| 189 | #define SPD_TRC_FTB 38 |
| 190 | |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 191 | /*----------------------------- |
| 192 | * Jedec DDR II related equates |
| 193 | *----------------------------- |
| 194 | */ |
| 195 | |
| 196 | #define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */ |
| 197 | #define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */ |
| 198 | |
| 199 | #define BIAS_TRTP_T 4 |
| 200 | #define BIAS_TRCD_T 5 |
| 201 | #define BIAS_TRAS_T 15 |
| 202 | #define BIAS_TRC_T 11 |
| 203 | #define BIAS_TRRD_T 4 |
| 204 | #define BIAS_TWR_T 4 |
| 205 | #define BIAS_TRP_T 5 |
| 206 | #define BIAS_TWTR_T 4 |
| 207 | #define BIAS_TFAW_T 14 |
| 208 | |
| 209 | #define MIN_TRTP_T 4 |
| 210 | #define MAX_TRTP_T 7 |
| 211 | #define MIN_TRCD_T 5 |
| 212 | #define MAX_TRCD_T 12 |
| 213 | #define MIN_TRAS_T 15 |
| 214 | #define MAX_TRAS_T 30 |
| 215 | #define MIN_TRC_T 11 |
| 216 | #define MAX_TRC_T 42 |
| 217 | #define MIN_TRRD_T 4 |
| 218 | #define MAX_TRRD_T 7 |
| 219 | #define MIN_TWR_T 5 |
| 220 | #define MAX_TWR_T 12 |
| 221 | #define MIN_TRP_T 5 |
| 222 | #define MAX_TRP_T 12 |
| 223 | #define MIN_TWTR_T 4 |
| 224 | #define MAX_TWTR_T 7 |
| 225 | #define MIN_TFAW_T 16 |
| 226 | #define MAX_TFAW_T 32 |
| 227 | |
| 228 | /*---------------------------------------------------------------------------- |
| 229 | * TYPEDEFS, STRUCTURES, ENUMS |
| 230 | * |
| 231 | *---------------------------------------------------------------------------- |
| 232 | */ |
| 233 | |
| 234 | /*---------------------------------------------------------------------------- |
| 235 | * FUNCTIONS PROTOTYPE |
| 236 | * |
| 237 | *---------------------------------------------------------------------------- |
| 238 | */ |
| 239 | |
| 240 | |
| 241 | #endif /* _MTSPD3_H_ */ |
| 242 | |
| 243 | |