Patrick Georgi | ea063cb | 2020-05-08 19:28:13 +0200 | [diff] [blame] | 1 | /* inteltool - dump all registers on an Intel CPU + chipset based system */ |
Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 3 | |
| 4 | #include <stdio.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <stdint.h> |
| 7 | #include <stdbool.h> |
| 8 | #include <inttypes.h> |
| 9 | #include <assert.h> |
| 10 | #include "pcr.h" |
| 11 | |
| 12 | const uint8_t *sbbar = NULL; |
| 13 | |
| 14 | uint32_t read_pcr32(const uint8_t port, const uint16_t offset) |
| 15 | { |
| 16 | assert(sbbar); |
| 17 | return *(const uint32_t *)(sbbar + (port << 16) + offset); |
| 18 | } |
| 19 | |
Youness Alaoui | d8214d7e | 2018-03-13 16:58:52 -0400 | [diff] [blame] | 20 | static void print_pcr_port(const uint8_t port) |
| 21 | { |
| 22 | size_t i = 0; |
| 23 | uint32_t last_reg = 0; |
| 24 | bool last_printed = true; |
| 25 | |
| 26 | printf("PCR port offset: 0x%06zx\n\n", (size_t)port << 16); |
| 27 | |
| 28 | for (i = 0; i < PCR_PORT_SIZE; i += 4) { |
| 29 | const uint32_t reg = read_pcr32(port, i); |
| 30 | const bool rep = i && last_reg == reg; |
| 31 | if (!rep) { |
| 32 | if (!last_printed) |
| 33 | printf("*\n"); |
| 34 | printf("0x%04zx: 0x%08"PRIx32"\n", i, reg); |
| 35 | } |
| 36 | |
| 37 | last_reg = reg; |
| 38 | last_printed = !rep; |
| 39 | } |
| 40 | if (!last_printed) |
| 41 | printf("*\n"); |
| 42 | } |
| 43 | |
| 44 | void print_pcr_ports(struct pci_dev *const sb, |
| 45 | const uint8_t *const ports, const size_t count) |
| 46 | { |
| 47 | size_t i; |
| 48 | |
| 49 | pcr_init(sb); |
| 50 | |
| 51 | for (i = 0; i < count; ++i) { |
| 52 | printf("\n========== PCR 0x%02x ==========\n\n", ports[i]); |
| 53 | print_pcr_port(ports[i]); |
| 54 | } |
| 55 | } |
| 56 | |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 57 | void pcr_init(struct pci_dev *const sb) |
| 58 | { |
| 59 | bool error_exit = false; |
| 60 | bool p2sb_revealed = false; |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 61 | struct pci_dev *p2sb; |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 62 | bool use_p2sb = true; |
| 63 | pciaddr_t sbbar_phys; |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 64 | |
| 65 | if (sbbar) |
| 66 | return; |
| 67 | |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 68 | switch (sb->device_id) { |
| 69 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE: |
Felix Singer | 0a7543d | 2019-02-19 23:49:11 +0100 | [diff] [blame] | 70 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: |
| 71 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: |
| 72 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: |
| 73 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: |
| 74 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: |
| 75 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: |
| 76 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: |
Shaleen Jain | 2822d66 | 2019-01-02 11:15:16 +0530 | [diff] [blame] | 77 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: |
| 78 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: |
| 79 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 80 | case PCI_DEVICE_ID_INTEL_H110: |
| 81 | case PCI_DEVICE_ID_INTEL_H170: |
| 82 | case PCI_DEVICE_ID_INTEL_Z170: |
| 83 | case PCI_DEVICE_ID_INTEL_Q170: |
| 84 | case PCI_DEVICE_ID_INTEL_Q150: |
| 85 | case PCI_DEVICE_ID_INTEL_B150: |
| 86 | case PCI_DEVICE_ID_INTEL_C236: |
| 87 | case PCI_DEVICE_ID_INTEL_C232: |
| 88 | case PCI_DEVICE_ID_INTEL_QM170: |
| 89 | case PCI_DEVICE_ID_INTEL_HM170: |
| 90 | case PCI_DEVICE_ID_INTEL_CM236: |
| 91 | case PCI_DEVICE_ID_INTEL_HM175: |
| 92 | case PCI_DEVICE_ID_INTEL_QM175: |
| 93 | case PCI_DEVICE_ID_INTEL_CM238: |
Timofey Komarov | 6c80082 | 2021-06-25 12:07:32 +0300 | [diff] [blame] | 94 | case PCI_DEVICE_ID_INTEL_H270: |
| 95 | case PCI_DEVICE_ID_INTEL_Z270: |
| 96 | case PCI_DEVICE_ID_INTEL_Q270: |
| 97 | case PCI_DEVICE_ID_INTEL_Q250: |
| 98 | case PCI_DEVICE_ID_INTEL_B250: |
| 99 | case PCI_DEVICE_ID_INTEL_Z370: |
| 100 | case PCI_DEVICE_ID_INTEL_H310C: |
| 101 | case PCI_DEVICE_ID_INTEL_X299: |
Maxim Polyakov | b89ce2e | 2019-08-17 14:54:02 +0300 | [diff] [blame] | 102 | case PCI_DEVICE_ID_INTEL_C621: |
Jingle Hsu | 4067fa3 | 2020-11-03 20:46:41 +0800 | [diff] [blame] | 103 | case PCI_DEVICE_ID_INTEL_C621A: |
Maxim Polyakov | b89ce2e | 2019-08-17 14:54:02 +0300 | [diff] [blame] | 104 | case PCI_DEVICE_ID_INTEL_C622: |
| 105 | case PCI_DEVICE_ID_INTEL_C624: |
| 106 | case PCI_DEVICE_ID_INTEL_C625: |
| 107 | case PCI_DEVICE_ID_INTEL_C626: |
| 108 | case PCI_DEVICE_ID_INTEL_C627: |
| 109 | case PCI_DEVICE_ID_INTEL_C628: |
| 110 | case PCI_DEVICE_ID_INTEL_C629: |
| 111 | case PCI_DEVICE_ID_INTEL_C624_SUPER: |
| 112 | case PCI_DEVICE_ID_INTEL_C627_SUPER_1: |
| 113 | case PCI_DEVICE_ID_INTEL_C621_SUPER: |
| 114 | case PCI_DEVICE_ID_INTEL_C627_SUPER_2: |
| 115 | case PCI_DEVICE_ID_INTEL_C628_SUPER: |
Thomas Heijligen | da02719 | 2019-01-12 19:20:50 +0100 | [diff] [blame] | 116 | case PCI_DEVICE_ID_INTEL_DNV_LPC: |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 117 | p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); |
| 118 | break; |
| 119 | case PCI_DEVICE_ID_INTEL_APL_LPC: |
Sean Rhodes | 645dde7 | 2021-10-22 09:31:22 +0100 | [diff] [blame] | 120 | case PCI_DEVICE_ID_INTEL_GLK_LPC: |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 121 | p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); |
| 122 | break; |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 123 | case PCI_DEVICE_ID_INTEL_H310: |
| 124 | case PCI_DEVICE_ID_INTEL_H370: |
| 125 | case PCI_DEVICE_ID_INTEL_Z390: |
| 126 | case PCI_DEVICE_ID_INTEL_Q370: |
| 127 | case PCI_DEVICE_ID_INTEL_B360: |
| 128 | case PCI_DEVICE_ID_INTEL_C246: |
| 129 | case PCI_DEVICE_ID_INTEL_C242: |
| 130 | case PCI_DEVICE_ID_INTEL_QM370: |
| 131 | case PCI_DEVICE_ID_INTEL_HM370: |
| 132 | case PCI_DEVICE_ID_INTEL_CM246: |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 133 | case PCI_DEVICE_ID_INTEL_Q570: |
| 134 | case PCI_DEVICE_ID_INTEL_Z590: |
| 135 | case PCI_DEVICE_ID_INTEL_H570: |
| 136 | case PCI_DEVICE_ID_INTEL_B560: |
| 137 | case PCI_DEVICE_ID_INTEL_H510: |
| 138 | case PCI_DEVICE_ID_INTEL_WM590: |
| 139 | case PCI_DEVICE_ID_INTEL_QM580: |
| 140 | case PCI_DEVICE_ID_INTEL_HM570: |
| 141 | case PCI_DEVICE_ID_INTEL_C252: |
| 142 | case PCI_DEVICE_ID_INTEL_C256: |
| 143 | case PCI_DEVICE_ID_INTEL_W580: |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 144 | case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: |
Matt DeVillier | 62e883d | 2020-08-08 11:17:31 -0500 | [diff] [blame] | 145 | case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: |
| 146 | case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: |
Johanna Schander | 0174ea7 | 2020-01-04 15:14:59 +0100 | [diff] [blame] | 147 | case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 148 | case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: |
| 149 | case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: |
| 150 | case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: |
| 151 | case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: |
| 152 | case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: |
Kacper Stojek | fb9110b | 2022-08-17 10:28:20 +0200 | [diff] [blame] | 153 | case PCI_DEVICE_ID_INTEL_ADL_P: |
| 154 | case PCI_DEVICE_ID_INTEL_ADL_M: |
| 155 | case PCI_DEVICE_ID_INTEL_RPL_P: |
Kacper Stojek | 76d2b66 | 2022-10-17 14:30:24 +0200 | [diff] [blame] | 156 | case PCI_DEVICE_ID_INTEL_EHL: |
Karol Zmyslowski | b2f5a22 | 2023-03-10 19:44:04 +0100 | [diff] [blame] | 157 | case PCI_DEVICE_ID_INTEL_JSL: |
Christian Walter | 1364ac3 | 2022-09-08 11:44:19 +0200 | [diff] [blame] | 158 | case PCI_DEVICE_ID_INTEL_EBG: |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 159 | sbbar_phys = 0xfd000000; |
| 160 | use_p2sb = false; |
| 161 | break; |
Maximilian Brune | 8d1051f | 2022-08-08 12:55:57 +0200 | [diff] [blame] | 162 | case PCI_DEVICE_ID_INTEL_H610E: |
| 163 | case PCI_DEVICE_ID_INTEL_Q670E: |
| 164 | case PCI_DEVICE_ID_INTEL_R680E: |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 165 | case PCI_DEVICE_ID_INTEL_H610: |
| 166 | case PCI_DEVICE_ID_INTEL_B660: |
| 167 | case PCI_DEVICE_ID_INTEL_H670: |
| 168 | case PCI_DEVICE_ID_INTEL_Q670: |
| 169 | case PCI_DEVICE_ID_INTEL_Z690: |
| 170 | case PCI_DEVICE_ID_INTEL_W680: |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 171 | case PCI_DEVICE_ID_INTEL_WM690: |
| 172 | case PCI_DEVICE_ID_INTEL_HM670: |
Michał Żygowski | 472d83b | 2023-06-16 12:49:12 +0200 | [diff] [blame] | 173 | case PCI_DEVICE_ID_INTEL_W790: |
| 174 | case PCI_DEVICE_ID_INTEL_Z790: |
| 175 | case PCI_DEVICE_ID_INTEL_H770: |
| 176 | case PCI_DEVICE_ID_INTEL_B760: |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 177 | case PCI_DEVICE_ID_INTEL_HM770: |
Michał Żygowski | 472d83b | 2023-06-16 12:49:12 +0200 | [diff] [blame] | 178 | case PCI_DEVICE_ID_INTEL_WM790: |
| 179 | case PCI_DEVICE_ID_INTEL_C262: |
| 180 | case PCI_DEVICE_ID_INTEL_C266: |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 181 | sbbar_phys = 0xe0000000; |
| 182 | use_p2sb = false; |
| 183 | break; |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 184 | default: |
| 185 | perror("Unknown LPC device."); |
| 186 | exit(1); |
| 187 | } |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 188 | |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 189 | if (use_p2sb) { |
| 190 | if (!p2sb) { |
| 191 | perror("Can't allocate device node for P2SB."); |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 192 | exit(1); |
| 193 | } |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 194 | |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 195 | /* do not fill bases here, libpci refuses to refill later */ |
| 196 | pci_fill_info(p2sb, PCI_FILL_IDENT); |
| 197 | if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) { |
| 198 | printf("Trying to reveal Primary to Sideband Bridge " |
| 199 | "(P2SB),\nlet's hope the OS doesn't mind... "); |
| 200 | /* Do not use pci_write_long(). Bytes |
| 201 | surrounding 0xe0 must be maintained. */ |
| 202 | pci_write_byte(p2sb, 0xe0 + 1, 0); |
| 203 | |
| 204 | pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN); |
| 205 | if (p2sb->vendor_id != 0xffff || |
| 206 | p2sb->device_id != 0xffff) { |
| 207 | printf("done.\n"); |
| 208 | p2sb_revealed = true; |
| 209 | } else { |
| 210 | printf("failed.\n"); |
| 211 | exit(1); |
| 212 | } |
| 213 | } |
| 214 | pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS); |
| 215 | |
| 216 | sbbar_phys = p2sb->base_addr[0] & ~0xfULL; |
| 217 | } |
| 218 | |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 219 | printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys); |
| 220 | sbbar = map_physical(sbbar_phys, SBBAR_SIZE); |
| 221 | if (sbbar == NULL) { |
| 222 | perror("Error mapping SBREG_BAR"); |
| 223 | error_exit = true; |
| 224 | } |
| 225 | |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 226 | if (use_p2sb) { |
| 227 | if (p2sb_revealed) { |
| 228 | printf("Hiding Primary to Sideband Bridge (P2SB).\n"); |
| 229 | pci_write_byte(p2sb, 0xe0 + 1, 1); |
| 230 | } |
| 231 | pci_free_dev(p2sb); |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 232 | } |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 233 | |
| 234 | if (error_exit) |
| 235 | exit(1); |
| 236 | } |
| 237 | |
| 238 | void pcr_cleanup(void) |
| 239 | { |
| 240 | if (sbbar) |
| 241 | unmap_physical((void *)sbbar, SBBAR_SIZE); |
| 242 | } |