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review.coreboot.org / coreboot / e132d5711df1bec0a83eb9deb0f892bb22579df6 / . / src / include / device / pci_ops.h
blob: 6971ce4de755aa663f4dd3b8a392d3493aedce22 [file] [log] [blame]
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]1#ifndef PCI_OPS_H
2#define PCI_OPS_H
3
4#include <stdint.h>
Eric Biederman7a5416a2003-06-12 19:23:51 +0000[diff] [blame]5#include <device/device.h>
Eric Biederman018d8dd2004-11-04 11:04:33 +0000[diff] [blame]6#include <arch/pci_ops.h>
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]7
Kyösti Mälkki92b52962019-03-01 08:08:28 +0200[diff] [blame]8#ifdef __SIMPLE_DEVICE__
9
10/* Avoid name collisions as different stages have different signature
11 * for these functions. The _s_ stands for simple, fundamental IO or
12 * MMIO variant.
13 */
14#define pci_read_config8 pci_s_read_config8
15#define pci_read_config16 pci_s_read_config16
16#define pci_read_config32 pci_s_read_config32
17#define pci_write_config8 pci_s_write_config8
18#define pci_write_config16 pci_s_write_config16
19#define pci_write_config32 pci_s_write_config32
20#else
Edward O'Callaghan016732f2014-10-29 03:04:40 +1100[diff] [blame]21u8 pci_read_config8(struct device *dev, unsigned int where);
22u16 pci_read_config16(struct device *dev, unsigned int where);
23u32 pci_read_config32(struct device *dev, unsigned int where);
24void pci_write_config8(struct device *dev, unsigned int where, u8 val);
25void pci_write_config16(struct device *dev, unsigned int where, u16 val);
26void pci_write_config32(struct device *dev, unsigned int where, u32 val);
Kyösti Mälkki78d14322019-01-23 15:57:49 +0200[diff] [blame]27const struct pci_bus_operations *pci_bus_default_ops(void);
Stefan Reinauer24d1d4b2013-03-21 11:51:41 -0700[diff] [blame]28#endif
Stefan Reinauer43b29cf2009-03-06 19:11:52 +0000[diff] [blame]29
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]30#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]31static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]32void pci_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask)
33#else
34static __always_inline
35void pci_or_config8(struct device *dev, unsigned int where, u8 ormask)
36#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]37{
38 u8 value = pci_read_config8(dev, where);
39 pci_write_config8(dev, where, value | ormask);
40}
41
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]42#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]43static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]44void pci_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask)
45#else
46static __always_inline
47void pci_or_config16(struct device *dev, unsigned int where, u16 ormask)
48#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]49{
50 u16 value = pci_read_config16(dev, where);
51 pci_write_config16(dev, where, value | ormask);
52}
53
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]54#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]55static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]56void pci_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask)
57#else
58static __always_inline
59void pci_or_config32(struct device *dev, unsigned int where, u32 ormask)
60#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]61{
62 u32 value = pci_read_config32(dev, where);
63 pci_write_config32(dev, where, value | ormask);
64}
65
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]66#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]67static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]68void pci_update_config8(pci_devfn_t dev, int reg, u8 mask, u8 or)
69#else
70static __always_inline
71void pci_update_config8(struct device *dev, int reg, u8 mask, u8 or)
72#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]73{
74 u8 reg8;
75
76 reg8 = pci_read_config8(dev, reg);
77 reg8 &= mask;
78 reg8 |= or;
79 pci_write_config8(dev, reg, reg8);
80}
81
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]82#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]83static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]84void pci_update_config16(pci_devfn_t dev, int reg, u16 mask, u16 or)
85#else
86static __always_inline
87void pci_update_config16(struct device *dev, int reg, u16 mask, u16 or)
88#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]89{
90 u16 reg16;
91
92 reg16 = pci_read_config16(dev, reg);
93 reg16 &= mask;
94 reg16 |= or;
95 pci_write_config16(dev, reg, reg16);
96}
97
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]98#ifdef __SIMPLE_DEVICE__
Aaron Durbin75a62e72018-09-13 02:10:45 -0600[diff] [blame]99static __always_inline
Elyes HAOUASf9e47cc2018-12-05 11:03:36 +0100[diff] [blame]100void pci_update_config32(pci_devfn_t dev, int reg, u32 mask, u32 or)
101#else
102static __always_inline
103void pci_update_config32(struct device *dev, int reg, u32 mask, u32 or)
104#endif
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]105{
106 u32 reg32;
107
108 reg32 = pci_read_config32(dev, reg);
109 reg32 &= mask;
110 reg32 |= or;
111 pci_write_config32(dev, reg, reg32);
112}
113
Eric Biederman5899fd82003-04-24 06:25:08 +0000[diff] [blame]114#endif /* PCI_OPS_H */