Jonathan A. Kollasch | 3e4f7a3 | 2020-01-10 13:23:02 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| 3 | |
| 4 | /* FIXME: Check if all includes are needed. */ |
| 5 | |
| 6 | #include <stdint.h> |
| 7 | #include <string.h> |
| 8 | #include <timestamp.h> |
| 9 | #include <arch/byteorder.h> |
| 10 | #include <device/mmio.h> |
| 11 | #include <device/pci_ops.h> |
| 12 | #include <device/pnp_def.h> |
| 13 | #include <device/pnp_ops.h> |
| 14 | #include <console/console.h> |
| 15 | #include <bootblock_common.h> |
| 16 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 17 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 18 | #include <southbridge/intel/bd82x6x/pch.h> |
| 19 | #include <southbridge/intel/common/gpio.h> |
| 20 | #include <superio/nuvoton/common/nuvoton.h> |
| 21 | #include <superio/nuvoton/nct6776/nct6776.h> |
| 22 | #include <superio/nuvoton/wpcm450/wpcm450.h> |
| 23 | #include "x9scl.h" |
| 24 | |
| 25 | #define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) |
| 26 | #define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11) |
| 27 | |
| 28 | #define SUPERIO_INITVAL(reg, data) {(reg), (data)} |
| 29 | #define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x)) |
| 30 | |
| 31 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 32 | { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ |
| 33 | { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ |
| 34 | { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ |
| 35 | { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ |
| 36 | { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ |
| 37 | { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ |
| 38 | { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ |
| 39 | { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ |
| 40 | { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ |
| 41 | { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ |
| 42 | { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ |
| 43 | { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ |
| 44 | { 1, 0, 5 }, |
| 45 | { 1, 0, 6 }, |
| 46 | }; |
| 47 | |
| 48 | static const uint8_t superio_initvals[][2] = { |
| 49 | /* Global config registers */ |
| 50 | SUPERIO_INITVAL(0x1a, 0xc8), |
| 51 | SUPERIO_INITVAL(0x1b, 0x68), |
| 52 | SUPERIO_INITVAL(0x1c, 0x83), |
| 53 | SUPERIO_INITVAL(0x24, 0x24), |
| 54 | //SUPERIO_INITVAL(0x27, 0x00), |
| 55 | SUPERIO_INITVAL(0x2a, 0x00), |
| 56 | SUPERIO_INITVAL(0x2b, 0x42), |
| 57 | SUPERIO_INITVAL(0x2c, 0x80), |
| 58 | |
| 59 | SUPERIO_BANK(0x9), /* GPIO[2345] */ |
| 60 | SUPERIO_INITVAL(0x30, 0x0c), |
| 61 | SUPERIO_INITVAL(0xe0, 0xcf), |
| 62 | SUPERIO_INITVAL(0xe4, 0xbd), |
| 63 | SUPERIO_INITVAL(0xe5, 0x42), |
| 64 | SUPERIO_INITVAL(0xe9, 0x10), |
| 65 | SUPERIO_INITVAL(0xea, 0x40), |
| 66 | SUPERIO_INITVAL(0xf0, 0xff), |
| 67 | SUPERIO_INITVAL(0xf1, 0x02), |
| 68 | |
| 69 | SUPERIO_BANK(0xb), /* HWM & LED */ |
| 70 | SUPERIO_INITVAL(0xf7, 0x07), |
| 71 | SUPERIO_INITVAL(0xf8, 0x40), |
| 72 | SUPERIO_INITVAL(0x30, 0x01), |
| 73 | SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8), |
| 74 | SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff), |
| 75 | |
| 76 | SUPERIO_BANK(0x5), /* KBC */ |
| 77 | SUPERIO_INITVAL(0xf0, 0x83), |
| 78 | SUPERIO_INITVAL(0x30, 0x01), |
| 79 | |
| 80 | SUPERIO_BANK(0x0), /* FDC */ |
| 81 | SUPERIO_INITVAL(0x30, 0x80), |
| 82 | |
| 83 | #if 0 |
| 84 | SUPERIO_BANK(8), |
| 85 | SUPERIO_INITVAL(0x30, 0x0a), |
| 86 | SUPERIO_INITVAL(0x60, X9SCL_NCT6776_GPIO_BASE >> 8), |
| 87 | SUPERIO_INITVAL(0x61, X9SCL_NCT6776_GPIO_BASE & 0xff), |
| 88 | SUPERIO_INITVAL(0xe1, 0xf9), |
| 89 | |
| 90 | SUPERIO_BANK(0xa), |
| 91 | SUPERIO_INITVAL(0xe4, 0x60), |
| 92 | #endif |
| 93 | }; |
| 94 | |
| 95 | |
| 96 | static void superio_init(void) |
| 97 | { |
| 98 | const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0); |
| 99 | |
| 100 | nuvoton_pnp_enter_conf_state(dev); |
| 101 | for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++) |
| 102 | pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]); |
| 103 | nuvoton_pnp_exit_conf_state(dev); |
| 104 | } |
| 105 | |
| 106 | static void bmc_init(void) |
| 107 | { |
| 108 | pnp_devfn_t dev = KCS_DEV; |
| 109 | |
| 110 | pnp_write_config(dev, 0x21, 0x11); |
| 111 | |
| 112 | pnp_set_logical_device(dev); |
| 113 | pnp_set_enable(dev, 0); |
| 114 | pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0); |
| 115 | pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1); |
| 116 | pnp_set_iobase(dev, PNP_IDX_IRQ0, 0); |
| 117 | pnp_set_enable(dev, 1); |
| 118 | |
| 119 | #if 0 |
| 120 | //wpcm450_enable_dev(WPCM450_SP2, X9SCL_WPCM450_PNP_BASE, 0x03e8); |
| 121 | //wpcm450_enable_dev(WPCM450_SP1, X9SCL_WPCM450_PNP_BASE, 0x02e8); |
| 122 | #endif |
| 123 | |
| 124 | #if 0 |
| 125 | dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP2); |
| 126 | pnp_set_logical_device(dev); |
| 127 | pnp_set_enable(dev, 0); |
| 128 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x03e8); |
| 129 | pnp_set_enable(dev, 1); |
| 130 | |
| 131 | dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP1); |
| 132 | pnp_set_logical_device(dev); |
| 133 | pnp_set_enable(dev, 0); |
| 134 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x02e8); |
| 135 | pnp_set_enable(dev, 0); |
| 136 | #endif |
| 137 | } |
| 138 | |
| 139 | void bootblock_mainboard_early_init(void) |
| 140 | { |
| 141 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 142 | superio_init(); |
| 143 | bmc_init(); |
| 144 | } |
| 145 | |
| 146 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 147 | { |
| 148 | read_spd(&spd[0], 0x50, id_only); |
| 149 | read_spd(&spd[1], 0x51, id_only); |
| 150 | read_spd(&spd[2], 0x52, id_only); |
| 151 | read_spd(&spd[3], 0x53, id_only); |
| 152 | } |
| 153 | |
| 154 | void mainboard_early_init(int s3resume) |
| 155 | { |
| 156 | /* Disable IGD VGA decode, no GTT or GFX stolen */ |
| 157 | pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); |
| 158 | } |