Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * JEDEC Standard No. 21-C |
| 5 | * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) |
| 6 | */ |
| 7 | |
| 8 | #ifndef DEVICE_DRAM_DDR2L_H |
| 9 | #define DEVICE_DRAM_DDR2L_H |
| 10 | |
| 11 | /** |
| 12 | * @file ddr2.h |
| 13 | * |
| 14 | * \brief Utilities for decoding DDR2 SPDs |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <spd.h> |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 19 | #include <device/dram/common.h> |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 20 | |
Martin Roth | 58964ff | 2023-10-23 09:59:09 -0600 | [diff] [blame] | 21 | /** Maximum SPD size supported */ |
| 22 | #define SPD_SIZE_MAX_DDR2 128 |
| 23 | |
Elyes Haouas | 5a04746 | 2022-12-28 11:43:49 +0100 | [diff] [blame] | 24 | /* Byte 20 [5:0]: DDR2 Module type information */ |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 25 | enum spd_dimm_type_ddr2 { |
Elyes Haouas | 5a04746 | 2022-12-28 11:43:49 +0100 | [diff] [blame] | 26 | SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, |
| 27 | SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, |
| 28 | SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, |
| 29 | SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 30 | SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06, |
| 31 | SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07, |
| 32 | SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08, |
| 33 | SPD_DDR2_DIMM_TYPE_MINI_RDIMM = 0x10, |
| 34 | SPD_DDR2_DIMM_TYPE_MINI_UDIMM = 0x20, |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 35 | /* Masks to bits 5:0 to give the dimm type */ |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 36 | SPD_DDR2_DIMM_TYPE_MASK = 0x3f, |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | /** |
| 40 | * \brief DIMM flags |
| 41 | * |
| 42 | * Characteristic flags for the DIMM, as presented by the SPD |
| 43 | */ |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 44 | union dimm_flags_ddr2_st { |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 45 | /* The whole point of the union/struct construct is to allow us to clear |
| 46 | * all the bits with one line: flags.raw = 0. |
| 47 | * We do not care how these bits are ordered */ |
| 48 | struct { |
| 49 | /* Module can work at 5.00V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 50 | unsigned int operable_5_00V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 51 | /* Module can work at 3.33V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 52 | unsigned int operable_3_33V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 53 | /* Module can work at 2.50V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 54 | unsigned int operable_2_50V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 55 | /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 56 | unsigned int operable_1_80V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 57 | /* Module can work at 1.50V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 58 | unsigned int operable_1_50V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 59 | /* Module can work at 1.35V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 60 | unsigned int operable_1_35V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 61 | /* Module can work at 1.20V */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 62 | unsigned int operable_1_25V:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 63 | /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 64 | unsigned int is_ecc:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 65 | /* Supports weak driver */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 66 | unsigned int weak_driver:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 67 | /* Supports terminating at 50 Ohm */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 68 | unsigned int terminate_50ohms:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 69 | /* Partial Array Self Refresh */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 70 | unsigned int pasr:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 71 | /* Supports burst length 8 */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 72 | unsigned int bl8:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 73 | /* Supports burst length 4 */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 74 | unsigned int bl4:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 75 | /* DIMM Package is stack */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 76 | unsigned int stacked:1; |
Arthur Heymans | 7eb0157 | 2017-09-21 08:28:23 +0200 | [diff] [blame] | 77 | /* the assembly supports self refresh */ |
Martin Roth | fc2047b | 2020-11-11 09:18:36 -0700 | [diff] [blame] | 78 | unsigned int self_refresh:1; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 79 | }; |
| 80 | unsigned int raw; |
| 81 | }; |
| 82 | |
| 83 | /** |
| 84 | * \brief DIMM characteristics |
| 85 | * |
| 86 | * The characteristics of each DIMM, as presented by the SPD |
| 87 | */ |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 88 | struct dimm_attr_ddr2_st { |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 89 | enum spd_memory_type dram_type; |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 90 | enum spd_dimm_type_ddr2 dimm_type; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 91 | /* BCD SPD revision */ |
| 92 | u8 rev; |
| 93 | /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */ |
| 94 | u8 cas_supported; |
Martin Roth | 3e25f85 | 2023-09-04 15:37:07 -0600 | [diff] [blame^] | 95 | /* Maximum clock to data cycle times for various CAS. |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 96 | * Fields 0 and 1 are unused. */ |
| 97 | u32 cycle_time[8]; |
| 98 | /* Maximum data access times for various CAS. |
| 99 | * Fields 0 and 1 are unused. */ |
| 100 | u32 access_time[8]; |
| 101 | /* Flags extracted from SPD */ |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 102 | union dimm_flags_ddr2_st flags; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 103 | /* Number of banks */ |
| 104 | u8 banks; |
| 105 | /* SDRAM width */ |
| 106 | u8 width; |
| 107 | /* Module width */ |
| 108 | u8 mod_width; |
| 109 | /* Number of ranks */ |
| 110 | u8 ranks; |
| 111 | /* Number or row address bits */ |
| 112 | u8 row_bits; |
| 113 | /* Number or column address bits */ |
| 114 | u8 col_bits; |
| 115 | /* Number of PLLs on module */ |
| 116 | u8 plls; |
| 117 | /* Size of module in MiB */ |
| 118 | u16 size_mb; |
| 119 | /* Size of one rank in MiB */ |
| 120 | u16 ranksize_mb; |
| 121 | /* Latencies are in units of 1/256 ns */ |
| 122 | u32 tCK; |
| 123 | u32 tWR; |
| 124 | u32 tRCD; |
| 125 | u32 tRRD; |
| 126 | u32 tRP; |
| 127 | u32 tRAS; |
| 128 | u32 tIS; |
| 129 | u32 tIH; |
| 130 | u32 tDS; |
| 131 | u32 tDH; |
| 132 | |
| 133 | u32 tRC; |
| 134 | u32 tRFC; |
| 135 | u32 tWTR; |
| 136 | u32 tRTP; |
| 137 | u32 tDQSQ; |
| 138 | u32 tQHS; |
| 139 | |
| 140 | /* Latencies are in units of 1/256 us */ |
| 141 | u32 tPLL; |
| 142 | u32 tRR; |
| 143 | |
Arthur Heymans | b5d4dd1 | 2017-09-25 12:47:41 +0200 | [diff] [blame] | 144 | u8 checksum; |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 145 | /* Manufacturer ID */ |
| 146 | u32 manufacturer_id; |
| 147 | /* ASCII part number - NULL terminated */ |
| 148 | u8 part_number[17]; |
| 149 | /* Year manufactured */ |
| 150 | u16 year; |
| 151 | /* Week manufactured */ |
| 152 | u8 weeks; |
| 153 | /* Unique serial number */ |
| 154 | u32 serial; |
| 155 | }; |
| 156 | |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 157 | int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type); |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 158 | u8 spd_ddr2_calc_checksum(u8 *spd, int len); |
| 159 | u32 spd_decode_spd_size_ddr2(u8 byte0); |
| 160 | u32 spd_decode_eeprom_size_ddr2(u8 byte1); |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 161 | int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); |
| 162 | void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm); |
Arthur Heymans | 3397aa1 | 2017-03-01 20:10:55 +0100 | [diff] [blame] | 163 | void normalize_tck(u32 *tclk); |
| 164 | u8 spd_get_msbs(u8 c); |
Arthur Heymans | 97b337b | 2018-01-22 01:26:53 +0100 | [diff] [blame] | 165 | u16 spd_ddr2_calc_unique_crc(const u8 *spd, int len); |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 166 | |
| 167 | #endif /* DEVICE_DRAM_DDR2L_H */ |