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review.coreboot.org / coreboot / 3e25f85d68d10249473d422c4c19dc30ea55e8b0 / . / src / drivers / mipi / panel-CMN_P097PFG_SSD2858.c
blob: 0336b63afe5393faf15acc6e49ea3c2bad4e29b6 [file] [log] [blame]
Julius Wernerb2a14802021-08-12 16:48:12 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Julius Werner5ff18082021-08-24 16:03:57 -0700[diff] [blame]3#include <mipi/panel.h>
Julius Wernerb2a14802021-08-12 16:48:12 -0700[diff] [blame]4
5struct panel_serializable_data P097PFG_SSD2858 = {
6 .edid = {
7 .ascii_string = "P097PFG",
8 .manufacturer_name = "CMN",
9 .panel_bits_per_color = 8,
10 .panel_bits_per_pixel = 24,
11 .mode = {
12 .pixel_clock = 211660,
13 .lvds_dual_channel = 0,
14 .refresh = 60,
15 .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10,
16 .va = 2048, .vbl = 32, .vso = 20, .vspw = 2,
17 .phsync = '-', .pvsync = '-',
18 .x_mm = 147, .y_mm = 196,
19 },
20 },
Julius Wernerb2a14802021-08-12 16:48:12 -0700[diff] [blame]21 .init = {
22 PANEL_GENERIC(0xff, 0x00),
23 /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
Martin Roth3e25f852023-09-04 15:37:07 -0600[diff] [blame^]24 * 27 MHz => 985.5 MHz */
Julius Wernerb2a14802021-08-12 16:48:12 -0700[diff] [blame]25 PANEL_GENERIC(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49),
26 /* MTXDIV=1, SYSDIV=3 (=> 4) */
27 PANEL_GENERIC(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03),
28 /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1,
29 * MRXEOT=1, MRXEE=1 */
30 PANEL_GENERIC(0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f),
31 PANEL_GENERIC(0x00, 0x20, 0x15, 0x92, 0x56, 0x7d),
32 PANEL_GENERIC(0x00, 0x24, 0x00, 0x00, 0x30, 0x00),
33
34 PANEL_GENERIC(0x10, 0x08, 0x01, 0x20, 0x08, 0x45),
35 PANEL_GENERIC(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00),
36 PANEL_GENERIC(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04),
Martin Roth3e25f852023-09-04 15:37:07 -0600[diff] [blame^]37 /* Pixel clock 985.5 MHz * 0x49/0x4b = 959 MHz */
Julius Wernerb2a14802021-08-12 16:48:12 -0700[diff] [blame]38 PANEL_GENERIC(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49),
39 PANEL_GENERIC(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00),
40 /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */
41 PANEL_GENERIC(0x60, 0x08, 0x00, 0xd9, 0x00, 0x08),
42 PANEL_GENERIC(0x60, 0x14, 0x01, 0x00, 0x01, 0x06),
43 /* DSI0 enable (default: probably not needed) */
44 PANEL_GENERIC(0x60, 0x80, 0x00, 0x00, 0x00, 0x0f),
45 /* DSI1 enable */
46 PANEL_GENERIC(0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f),
47
48 /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */
49 PANEL_GENERIC(0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18),
50 /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */
51 PANEL_GENERIC(0x60, 0x10, 0x08, 0x00, 0x14, 0x50),
52 /* HACT=0x300 (768) */
53 PANEL_GENERIC(0x60, 0x84, 0x00, 0x00, 0x03, 0x00),
54 PANEL_GENERIC(0x60, 0xa4, 0x00, 0x00, 0x03, 0x00),
55
56 /* Take panel out of sleep. */
57 PANEL_GENERIC(0xff, 0x01),
58 PANEL_DCS(0x11),
59 PANEL_DELAY(120),
60 PANEL_DCS(0x29),
61 PANEL_DELAY(20),
62 PANEL_GENERIC(0xff, 0x00),
63
64 PANEL_DELAY(120),
65 PANEL_DCS(0x11),
66 PANEL_DELAY(120),
67 PANEL_DCS(0x29),
68 PANEL_DELAY(20),
69 PANEL_END,
70 },
71};