Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <cpu/cpu.h> |
| 21 | #include <cpu/x86/mtrr.h> |
| 22 | #include <cpu/x86/msr.h> |
| 23 | #include <cpu/x86/lapic.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 24 | #include <cpu/intel/hyperthreading.h> |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 25 | #include <cpu/intel/microcode.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 26 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 27 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 28 | #include <cpu/x86/name.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 29 | #include <cpu/intel/common/common.h> |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 30 | |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 31 | #define HIGHEST_CLEVEL 3 |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 32 | static void configure_c_states(void) |
| 33 | { |
| 34 | msr_t msr; |
| 35 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 36 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 37 | msr.lo |= (1 << 15); // config lock until next reset |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 38 | msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 39 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 40 | msr.lo |= (1 << 3); // dynamic L2 |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 41 | |
| 42 | /* Number of supported C-States */ |
| 43 | msr.lo &= ~7; |
| 44 | msr.lo |= HIGHEST_CLEVEL; // support at most C3 |
| 45 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 46 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 47 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 48 | /* Set Processor MWAIT IO BASE (P_BLK) */ |
| 49 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 50 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) |
| 51 | << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 52 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 53 | |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 54 | /* Set C_LVL controls and IO Capture Address */ |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 55 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 56 | // -2 because LVL0+1 aren't counted |
| 57 | msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 58 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | #define IA32_MISC_ENABLE 0x1a0 |
| 62 | static void configure_misc(void) |
| 63 | { |
| 64 | msr_t msr; |
| 65 | |
| 66 | msr = rdmsr(IA32_MISC_ENABLE); |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 67 | msr.lo |= (1 << 3); /* TM1 enable */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 68 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 69 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 70 | |
| 71 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 72 | |
| 73 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 74 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 75 | |
Arthur Heymans | aacd548 | 2016-10-06 12:14:14 +0200 | [diff] [blame] | 76 | /* Enable C2E */ |
| 77 | msr.lo |= (1 << 26); |
| 78 | |
| 79 | /* Enable C4E */ |
| 80 | msr.hi |= (1 << (32 - 32)); // C4E |
| 81 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 82 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 83 | wrmsr(IA32_MISC_ENABLE, msr); |
| 84 | |
| 85 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 86 | wrmsr(IA32_MISC_ENABLE, msr); |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 87 | |
| 88 | // set maximum CPU speed |
| 89 | msr = rdmsr(IA32_PERF_STS); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 90 | int busratio_max = (msr.hi >> (40-32)) & 0x1f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 91 | |
| 92 | msr = rdmsr(IA32_PLATFORM_ID); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 93 | int vid_max = msr.lo & 0x3f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 94 | |
| 95 | msr.lo &= ~0xffff; |
| 96 | msr.lo |= busratio_max << 8; |
| 97 | msr.lo |= vid_max; |
| 98 | |
| 99 | wrmsr(IA32_PERF_CTL, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 102 | #define PIC_SENS_CFG 0x1aa |
| 103 | static void configure_pic_thermal_sensors(void) |
| 104 | { |
| 105 | msr_t msr; |
| 106 | |
| 107 | msr = rdmsr(PIC_SENS_CFG); |
| 108 | |
| 109 | msr.lo |= (1 << 21); // inter-core lock TM1 |
| 110 | msr.lo |= (1 << 4); // Enable bypass filter |
| 111 | |
| 112 | wrmsr(PIC_SENS_CFG, msr); |
| 113 | } |
| 114 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 115 | static void model_6ex_init(struct device *cpu) |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 116 | { |
| 117 | char processor_name[49]; |
| 118 | |
| 119 | /* Turn on caching if we haven't already */ |
| 120 | x86_enable_cache(); |
| 121 | |
| 122 | /* Update the microcode */ |
Alexandru Gagniuc | 2c38f50 | 2013-12-06 23:14:54 -0600 | [diff] [blame] | 123 | intel_update_microcode_from_cbfs(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 124 | |
| 125 | /* Print processor name */ |
| 126 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 127 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 128 | |
| 129 | /* Setup MTRRs */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 130 | x86_setup_mtrrs(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 131 | x86_mtrr_check(); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 132 | |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 133 | /* Setup Page Attribute Tables (PAT) */ |
| 134 | // TODO set up PAT |
| 135 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 136 | /* Enable the local CPU APICs */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 137 | setup_lapic(); |
| 138 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 139 | /* Set virtualization based on Kconfig option */ |
| 140 | set_vmx(); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 141 | |
| 142 | /* Configure C States */ |
| 143 | configure_c_states(); |
| 144 | |
| 145 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 146 | configure_misc(); |
| 147 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 148 | /* PIC thermal sensor control */ |
| 149 | configure_pic_thermal_sensors(); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 150 | |
Elyes HAOUAS | d82be92 | 2016-07-28 18:58:27 +0200 | [diff] [blame] | 151 | /* Start up my CPU siblings */ |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 152 | intel_sibling_init(cpu); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static struct device_operations cpu_dev_ops = { |
| 156 | .init = model_6ex_init, |
| 157 | }; |
| 158 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 159 | static const struct cpu_device_id cpu_table[] = { |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 160 | { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */ |
| 161 | { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 162 | { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 163 | { 0, 0 }, |
| 164 | }; |
| 165 | |
| 166 | static const struct cpu_driver driver __cpu_driver = { |
| 167 | .ops = &cpu_dev_ops, |
| 168 | .id_table = cpu_table, |
| 169 | }; |