Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | # Warning: This file is included whether or not the if is here. |
| 2 | # The if controls how the evaluation occurs. |
| 3 | # (See also src/Kconfig) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 4 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 5 | source "src/cpu/*/Kconfig" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 6 | |
Furquan Shaikh | fd33781 | 2014-04-22 15:16:54 -0700 | [diff] [blame] | 7 | if ARCH_X86 |
| 8 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 9 | config DCACHE_RAM_BASE |
| 10 | hex |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 11 | |
| 12 | config DCACHE_RAM_SIZE |
| 13 | hex |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 14 | |
Timothy Pearson | b5e4655 | 2015-06-02 13:47:36 -0500 | [diff] [blame] | 15 | config DCACHE_BSP_STACK_SIZE |
| 16 | hex |
| 17 | |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 18 | config EARLYRAM_BSP_STACK_SIZE |
| 19 | depends on RESET_VECTOR_IN_RAM |
| 20 | hex |
| 21 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 22 | config SMP |
| 23 | bool |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 24 | default y if MAX_CPUS != 1 |
Patrick Georgi | 892b091 | 2009-09-24 09:03:06 +0000 | [diff] [blame] | 25 | default n |
Uwe Hermann | a29ad5c | 2009-10-18 18:35:50 +0000 | [diff] [blame] | 26 | help |
| 27 | This option is used to enable certain functions to make coreboot |
| 28 | work correctly on symmetric multi processor (SMP) systems. |
Ronald G. Minnich | 149d675 | 2009-10-01 23:22:50 +0000 | [diff] [blame] | 29 | |
Ronald G. Minnich | 149d675 | 2009-10-01 23:22:50 +0000 | [diff] [blame] | 30 | config SSE |
| 31 | bool |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 32 | help |
| 33 | Select SSE in your socket or model Kconfig if your CPU has SSE |
Elyes HAOUAS | 32fecd6 | 2020-02-22 10:15:33 +0100 | [diff] [blame] | 34 | streaming SIMD instructions. |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 35 | |
| 36 | config SSE2 |
| 37 | bool |
Myles Watson | 3426195 | 2010-03-19 02:33:40 +0000 | [diff] [blame] | 38 | default n |
Aaron Durbin | b1aa611 | 2017-06-16 15:20:57 -0500 | [diff] [blame] | 39 | select SSE |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 40 | help |
| 41 | Select SSE2 in your socket or model Kconfig if your CPU has SSE2 |
| 42 | streaming SIMD instructions. Some parts of coreboot can be built |
| 43 | with more efficient code if SSE2 instructions are available. |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 44 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 45 | endif # ARCH_X86 |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 46 | |
Alexandru Gagniuc | 66e0c4c | 2013-12-04 22:21:15 -0600 | [diff] [blame] | 47 | config SUPPORT_CPU_UCODE_IN_CBFS |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 48 | bool |
| 49 | default n |
| 50 | |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 51 | config USES_MICROCODE_HEADER_FILES |
| 52 | def_bool n |
| 53 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 54 | help |
| 55 | This is selected by a board or chipset to set the default for the |
| 56 | microcode source choice to a list of external microcode headers |
| 57 | |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 58 | config MICROCODE_BLOB_NOT_IN_BLOB_REPO |
| 59 | bool |
| 60 | help |
| 61 | Selected by platforms that don't maintain microcode updates in the |
| 62 | blobs repo yet. |
| 63 | |
| 64 | config MICROCODE_BLOB_NOT_HOOKED_UP |
| 65 | bool |
| 66 | help |
| 67 | Selected by platforms that haven't hooked microcode updates up yet. |
| 68 | |
| 69 | config MICROCODE_BLOB_UNDISCLOSED |
| 70 | bool |
| 71 | help |
| 72 | Selected by work-in-progress platforms that don't have microcode |
| 73 | updates available yet. |
| 74 | |
| 75 | config USE_CPU_MICROCODE_CBFS_BINS |
| 76 | bool |
| 77 | help |
| 78 | Automatically selected below to add binary microcode files |
| 79 | (`cpu_microcode_bins` in the makefiles) to CBFS. |
| 80 | |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 81 | choice |
Stefan Reinauer | 9c29cfa | 2013-02-27 20:24:11 +0100 | [diff] [blame] | 82 | prompt "Include CPU microcode in CBFS" if ARCH_X86 |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 83 | default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 84 | default CPU_MICROCODE_CBFS_NONE if MICROCODE_BLOB_NOT_IN_BLOB_REPO || \ |
| 85 | MICROCODE_BLOB_NOT_HOOKED_UP || \ |
| 86 | MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 3c1b7b4 | 2023-05-20 16:28:18 +0530 | [diff] [blame^] | 87 | depends on SUPPORT_CPU_UCODE_IN_CBFS && !CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 88 | |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 89 | config CPU_MICROCODE_CBFS_DEFAULT_BINS |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 90 | bool "Generate from tree" |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 91 | select USE_CPU_MICROCODE_CBFS_BINS |
| 92 | depends on !(MICROCODE_BLOB_NOT_IN_BLOB_REPO || \ |
| 93 | MICROCODE_BLOB_NOT_HOOKED_UP || \ |
| 94 | MICROCODE_BLOB_UNDISCLOSED) |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 95 | help |
| 96 | Select this option if you want microcode updates to be assembled when |
| 97 | building coreboot and included in the final image as a separate CBFS |
| 98 | file. Microcode will not be hard-coded into ramstage. |
| 99 | |
Stefan Tauner | 0ce2b43 | 2013-04-01 13:45:44 +0200 | [diff] [blame] | 100 | The microcode file may be removed from the ROM image at a later |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 101 | time with cbfstool, if desired. |
| 102 | |
| 103 | If unsure, select this option. |
| 104 | |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 105 | config CPU_MICROCODE_CBFS_EXTERNAL_BINS |
| 106 | bool "Include external microcode binary" |
| 107 | select USE_CPU_MICROCODE_CBFS_BINS |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 108 | help |
| 109 | Select this option if you want to include external binary files |
| 110 | in the CPUs native format. They will be included as a separate |
| 111 | file in CBFS. |
| 112 | |
| 113 | A word of caution: only select this option if you are sure the |
| 114 | microcode that you have is newer than the microcode shipping with |
| 115 | coreboot. |
| 116 | |
| 117 | The microcode file may be removed from the ROM image at a later |
| 118 | time with cbfstool, if desired. |
| 119 | |
| 120 | If unsure, and applicable, select "Generate from tree" |
| 121 | |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 122 | config CPU_MICROCODE_CBFS_EXTERNAL_HEADER |
| 123 | bool "Include external microcode header files" |
| 124 | help |
| 125 | Select this option if you want to include external c header files |
| 126 | containing the CPU microcode. This will be included as a separate |
| 127 | file in CBFS. |
| 128 | |
| 129 | A word of caution: only select this option if you are sure the |
| 130 | microcode that you have is newer than the microcode shipping with |
| 131 | coreboot. |
| 132 | |
| 133 | The microcode file may be removed from the ROM image at a later |
| 134 | time with cbfstool, if desired. |
| 135 | |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 136 | If unsure, and applicable, select "Generate from tree" |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 137 | |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 138 | config CPU_MICROCODE_CBFS_NONE |
| 139 | bool "Do not include microcode updates" |
| 140 | help |
| 141 | Select this option if you do not want CPU microcode included in CBFS. |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 142 | |
| 143 | Microcode may be added to the ROM image at a later time with cbfstool, |
| 144 | if desired. |
| 145 | |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 146 | If unsure, and applicable, select "Generate from tree" |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 147 | |
| 148 | The GOOD: |
| 149 | Microcode updates intend to solve issues that have been discovered |
| 150 | after CPU production. The expected effect is that systems work as |
| 151 | intended with the updated microcode, but we have also seen cases where |
| 152 | issues were solved by not applying microcode updates. |
| 153 | |
| 154 | The BAD: |
| 155 | Note that some operating system include these same microcode patches, |
| 156 | so you may need to also disable microcode updates in your operating |
| 157 | system for this option to have an effect. |
| 158 | |
| 159 | The UGLY: |
| 160 | A word of CAUTION: some CPUs depend on microcode updates to function |
| 161 | correctly. Not updating the microcode may leave the CPU operating at |
| 162 | less than optimal performance, or may cause outright hangups. |
| 163 | There are CPUs where coreboot cannot properly initialize the CPU |
| 164 | without microcode updates |
| 165 | For example, if running with the factory microcode, some Intel |
| 166 | SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs |
| 167 | will hang when changing the frequency. |
| 168 | |
| 169 | Make sure you have a way of flashing the ROM externally before |
| 170 | selecting this option. |
| 171 | |
| 172 | endchoice |
Jens Rottmann | 686dc0d | 2013-02-18 17:26:01 +0100 | [diff] [blame] | 173 | |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 174 | config CPU_MICROCODE_HEADER_FILES |
| 175 | string "List of space separated microcode header files with the path" |
| 176 | depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER |
| 177 | help |
| 178 | A list of one or more microcode header files with path from the |
| 179 | coreboot directory. These should be separated by spaces. |
Martin Roth | 3eb65ec | 2016-08-30 16:21:53 -0600 | [diff] [blame] | 180 | |
| 181 | config CPU_UCODE_BINARIES |
| 182 | string "Microcode binary path and filename" |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 183 | depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS |
Martin Roth | 3eb65ec | 2016-08-30 16:21:53 -0600 | [diff] [blame] | 184 | default "" |
| 185 | help |
| 186 | Some platforms have microcode in the blobs directory, and these can |
| 187 | be hardcoded in the makefiles. For platforms with microcode |
| 188 | binaries that aren't in the makefile, set this option to pull |
| 189 | in the microcode. |
| 190 | |
| 191 | This should contain the full path of the file for one or more |
| 192 | microcode binary files to include, separated by spaces. |
| 193 | |
| 194 | If unsure, leave this blank. |