blob: da35daecd8255d12bd18fc4f909cf3012b6eed24 [file] [log] [blame]
Felix Helddba3fe72021-02-13 01:05:56 +01001config SOC_AMD_COMMON_BLOCK_DATA_FABRIC
2 bool
3 help
4 Select this option to add data fabric configuration related
5 functionality to the build.
Felix Held407bd582023-04-24 17:58:24 +02006
Felix Heldd6326972023-09-15 22:40:02 +02007config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION
8 bool
9 depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC
10 help
11 Select this option to include the code to make sure that there's a
12 non-posted MMIO region configured in the data fabric registers that
13 covers the FCH MMIO from the HPET up to right below the LAPIC.
14
Felix Held407bd582023-04-24 17:58:24 +020015config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
16 bool
17 depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC
Felix Held32169722023-07-14 19:41:06 +020018 select SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX
Felix Held407bd582023-04-24 17:58:24 +020019 help
20 Select this option to add functionality to the build to tell the
21 resource allocator about the MMIO regions configured in the data
22 fabric registers so that it knows in which regions it can properly
23 allocate the non-fixed MMIO devices.
Felix Heldea831392023-08-08 02:55:09 +020024
25config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
26 bool
27 depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
28 help
29 Some AMD SoCs support more than one PCI segment with 256 buses. Those
30 SoCs however have a different data fabric register layout for the PCI
31 bus number decoding. SoCs that use a data fabric register pair for
32 the PCI bus number which includes the segment number must select this
33 option; SoCs that use one data fabric register for the PCI bus number
34 which doesn't include a segment number field mustn't select this.
Felix Held7cdc4292023-08-28 14:31:16 +020035
36config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
37 bool
38 depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
39 help
40 Some AMD SoCs support more than 48 bit MMIO addresses. In order to
41 have enough bits for this, the MMIO address extension register is
42 introduced. SoCs that have this register must select this option in
43 order for the MMIO regions to be reported correctly.