Patrick Georgi | d1e50f9 | 2020-03-04 15:00:05 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Early initialization code for riscv |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <bits.h> |
Ronald G. Minnich | 6f3a53b | 2017-01-15 17:40:51 +0100 | [diff] [blame] | 7 | #include <mcall.h> |
| 8 | |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 9 | .macro restore_regs |
| 10 | # restore x registers |
| 11 | LOAD x1,1*REGBYTES(a0) |
| 12 | LOAD x2,2*REGBYTES(a0) |
| 13 | LOAD x3,3*REGBYTES(a0) |
| 14 | LOAD x4,4*REGBYTES(a0) |
| 15 | LOAD x5,5*REGBYTES(a0) |
| 16 | LOAD x6,6*REGBYTES(a0) |
| 17 | LOAD x7,7*REGBYTES(a0) |
| 18 | LOAD x8,8*REGBYTES(a0) |
| 19 | LOAD x9,9*REGBYTES(a0) |
| 20 | LOAD x11,11*REGBYTES(a0) |
| 21 | LOAD x12,12*REGBYTES(a0) |
| 22 | LOAD x13,13*REGBYTES(a0) |
| 23 | LOAD x14,14*REGBYTES(a0) |
| 24 | LOAD x15,15*REGBYTES(a0) |
| 25 | LOAD x16,16*REGBYTES(a0) |
| 26 | LOAD x17,17*REGBYTES(a0) |
| 27 | LOAD x18,18*REGBYTES(a0) |
| 28 | LOAD x19,19*REGBYTES(a0) |
| 29 | LOAD x20,20*REGBYTES(a0) |
| 30 | LOAD x21,21*REGBYTES(a0) |
| 31 | LOAD x22,22*REGBYTES(a0) |
| 32 | LOAD x23,23*REGBYTES(a0) |
| 33 | LOAD x24,24*REGBYTES(a0) |
| 34 | LOAD x25,25*REGBYTES(a0) |
| 35 | LOAD x26,26*REGBYTES(a0) |
| 36 | LOAD x27,27*REGBYTES(a0) |
| 37 | LOAD x28,28*REGBYTES(a0) |
| 38 | LOAD x29,29*REGBYTES(a0) |
| 39 | LOAD x30,30*REGBYTES(a0) |
| 40 | LOAD x31,31*REGBYTES(a0) |
| 41 | # restore a0 last |
| 42 | LOAD x10,10*REGBYTES(a0) |
| 43 | |
| 44 | |
| 45 | .endm |
| 46 | .macro save_tf |
| 47 | # save gprs |
| 48 | STORE x1,1*REGBYTES(x2) |
| 49 | STORE x3,3*REGBYTES(x2) |
| 50 | STORE x4,4*REGBYTES(x2) |
| 51 | STORE x5,5*REGBYTES(x2) |
| 52 | STORE x6,6*REGBYTES(x2) |
| 53 | STORE x7,7*REGBYTES(x2) |
| 54 | STORE x8,8*REGBYTES(x2) |
| 55 | STORE x9,9*REGBYTES(x2) |
| 56 | STORE x10,10*REGBYTES(x2) |
| 57 | STORE x11,11*REGBYTES(x2) |
| 58 | STORE x12,12*REGBYTES(x2) |
| 59 | STORE x13,13*REGBYTES(x2) |
| 60 | STORE x14,14*REGBYTES(x2) |
| 61 | STORE x15,15*REGBYTES(x2) |
| 62 | STORE x16,16*REGBYTES(x2) |
| 63 | STORE x17,17*REGBYTES(x2) |
| 64 | STORE x18,18*REGBYTES(x2) |
| 65 | STORE x19,19*REGBYTES(x2) |
| 66 | STORE x20,20*REGBYTES(x2) |
| 67 | STORE x21,21*REGBYTES(x2) |
| 68 | STORE x22,22*REGBYTES(x2) |
| 69 | STORE x23,23*REGBYTES(x2) |
| 70 | STORE x24,24*REGBYTES(x2) |
| 71 | STORE x25,25*REGBYTES(x2) |
| 72 | STORE x26,26*REGBYTES(x2) |
| 73 | STORE x27,27*REGBYTES(x2) |
| 74 | STORE x28,28*REGBYTES(x2) |
| 75 | STORE x29,29*REGBYTES(x2) |
| 76 | STORE x30,30*REGBYTES(x2) |
| 77 | STORE x31,31*REGBYTES(x2) |
| 78 | |
| 79 | # get sr, epc, badvaddr, cause |
| 80 | csrrw t0,mscratch,x0 |
| 81 | csrr s0,mstatus |
| 82 | csrr t1,mepc |
| 83 | csrr t2,mbadaddr |
| 84 | csrr t3,mcause |
| 85 | STORE t0,2*REGBYTES(x2) |
| 86 | STORE s0,32*REGBYTES(x2) |
| 87 | STORE t1,33*REGBYTES(x2) |
| 88 | STORE t2,34*REGBYTES(x2) |
| 89 | STORE t3,35*REGBYTES(x2) |
| 90 | |
| 91 | # get faulting insn, if it wasn't a fetch-related trap |
| 92 | li x5,-1 |
| 93 | STORE x5,36*REGBYTES(x2) |
Ronald G. Minnich | 6f3a53b | 2017-01-15 17:40:51 +0100 | [diff] [blame] | 94 | |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 95 | .endm |
| 96 | |
Ronald G. Minnich | 6f3a53b | 2017-01-15 17:40:51 +0100 | [diff] [blame] | 97 | .globl estack |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 98 | .text |
Jonathan Neuschäfer | 64d855d | 2017-09-29 01:37:00 +0200 | [diff] [blame] | 99 | |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 100 | .global trap_entry |
Jonathan Neuschäfer | 27d3402 | 2018-01-08 18:31:42 +0100 | [diff] [blame] | 101 | .align 2 # four byte alignment, as required by mtvec |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 102 | trap_entry: |
| 103 | csrw mscratch, sp |
Jonathan Neuschäfer | 4d6ef3a | 2016-08-11 22:49:10 +0200 | [diff] [blame] | 104 | |
| 105 | # SMP isn't supported yet, to avoid overwriting the same stack with different |
| 106 | # harts that handle traps at the same time. |
Ronald G. Minnich | 571c230 | 2016-10-28 15:08:59 -0700 | [diff] [blame] | 107 | # someday this gets fixed. |
| 108 | //csrr sp, mhartid |
| 109 | csrr sp, 0xf14 |
Jonathan Neuschäfer | 4d6ef3a | 2016-08-11 22:49:10 +0200 | [diff] [blame] | 110 | .Lsmp_hang: |
| 111 | bnez sp, .Lsmp_hang |
| 112 | |
Elyes Haouas | 3b3bb7c | 2023-02-08 12:49:33 +0100 | [diff] [blame^] | 113 | # Use a different stack than in the main context, to avoid overwriting |
Jonathan Neuschäfer | 5a6e389 | 2017-09-26 01:44:46 +0200 | [diff] [blame] | 114 | # stack data. |
| 115 | # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if |
| 116 | # the previous mode was M, because it would be a very bad idea to use a stack |
| 117 | # pointer provided by unprivileged code! |
| 118 | la sp, _estack |
| 119 | addi sp, sp, -2048 # 2 KiB is half of the stack space |
| 120 | addi sp, sp, -MENTRY_FRAME_SIZE |
Jonathan Neuschäfer | 4d6ef3a | 2016-08-11 22:49:10 +0200 | [diff] [blame] | 121 | |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 122 | save_tf |
Thaminda Edirisooriya | 31f0521 | 2015-08-26 12:22:29 -0700 | [diff] [blame] | 123 | move a0,sp |
| 124 | jal trap_handler |
Jonathan Neuschäfer | 3f75f5d | 2017-11-24 23:12:14 +0100 | [diff] [blame] | 125 | |
Jonathan Neuschäfer | 3f75f5d | 2017-11-24 23:12:14 +0100 | [diff] [blame] | 126 | trap_return: |
| 127 | csrr a0, mscratch |
| 128 | restore_regs |
| 129 | # go back to the previous mode |
| 130 | mret |