Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Lee Leahy | b993d2f | 2015-07-17 11:07:54 -0700 | [diff] [blame] | 18 | * Foundation, Inc. |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
robbie zhang | c9d9729 | 2015-08-21 09:47:34 -0700 | [diff] [blame] | 21 | #ifndef MAINBOARD_GPIO_H |
| 22 | #define MAINBOARD_GPIO_H |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 23 | |
| 24 | #include <soc/gpio.h> |
| 25 | |
Wenkai Du | 1105fad | 2015-08-21 13:11:00 -0700 | [diff] [blame^] | 26 | /* Pad configuration in ramstage. */ |
robbie zhang | c9d9729 | 2015-08-21 09:47:34 -0700 | [diff] [blame] | 27 | static const struct pad_config gpio_table[] = { |
| 28 | /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), |
| 29 | /* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), |
| 30 | /* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), |
| 31 | /* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), |
| 32 | /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), |
| 33 | /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), |
| 34 | /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), |
| 35 | /* PIRQA# */ /* GPP_A7 */ |
| 36 | /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), |
| 37 | /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), |
| 38 | /* PCH_LPC_CLK */ /* GPP_A10 */ |
| 39 | /* EC_HID_INT */ /* GPP_A11 */ |
| 40 | /* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP), |
| 41 | /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), |
| 42 | /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), |
| 43 | /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), |
| 44 | /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), |
| 45 | /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), |
| 46 | /* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 47 | /* ISH_GP1 */ /* GPP_A19 */ |
| 48 | /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), |
| 49 | /* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), |
| 50 | /* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), |
| 51 | /* ISH_GP5 */ /* GPP_A23 */ |
| 52 | /* CORE_VID0 */ /* GPP_B0 */ |
| 53 | /* CORE_VID1 */ /* GPP_B1 */ |
| 54 | /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), |
| 55 | /* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), |
| 56 | /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), |
| 57 | /* SRCCLKREQ0# */ /* GPP_B5 */ |
| 58 | /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), |
| 59 | /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), |
| 60 | /* SRCCLKREQ3# */ /* GPP_B8 */ |
| 61 | /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), |
| 62 | /* SRCCLKREQ5# */ /* GPP_B10 */ |
| 63 | /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), |
| 64 | /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 65 | /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 66 | /* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), |
| 67 | /* GSPI0_CS# */ /* GPP_B15 */ |
| 68 | /* WLAN_PCIE_WAKE */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), |
| 69 | /* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), |
| 70 | /* GSPI0_MOSI */ /* GPP_B18 */ |
| 71 | /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), |
| 72 | /* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), |
| 73 | /* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), |
| 74 | /* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), |
| 75 | /* SM1ALERT# */ /* GPP_B23 */ |
| 76 | /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), |
| 77 | /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), |
| 78 | /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), |
| 79 | /* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP), |
| 80 | /* SML0DATA */ /* GPP_C4 */ |
| 81 | /* SML0ALERT# */ /* GPP_C5 */ |
| 82 | /* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), |
| 83 | /* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP), |
| 84 | /* UART0_RXD */ /* GPP_C8 */ |
| 85 | /* UART0_TXD */ /* GPP_C9 */ |
| 86 | /* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP), |
| 87 | /* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP), |
| 88 | /* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), |
| 89 | /* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), |
| 90 | /* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), |
| 91 | /* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), |
| 92 | /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), |
| 93 | /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), |
| 94 | /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 95 | /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 96 | /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 97 | /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 98 | /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), |
| 99 | /* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), |
| 100 | /* ITCH_SPI_CS */ /* GPP_D0 */ |
| 101 | /* ITCH_SPI_CLK */ /* GPP_D1 */ |
| 102 | /* ITCH_SPI_MISO_1 */ /* GPP_D2 */ |
| 103 | /* ITCH_SPI_MISO_0 */ /* GPP_D3 */ |
| 104 | /* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), |
| 105 | /* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP), |
| 106 | /* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP), |
| 107 | /* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 108 | /* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 109 | PAD_CFG_GPO(GPP_D9, 0, DEEP), |
| 110 | /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP), |
| 111 | /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP), |
| 112 | /* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP), |
| 113 | /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), |
| 114 | /* ISH_UART0_TXD */ /* GPP_D14 */ |
| 115 | /* ISH_UART0_RTS */ /* GPP_D15 */ |
| 116 | /* ISH_UART0_CTS */ /* GPP_D16 */ |
| 117 | /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), |
| 118 | /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), |
| 119 | /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 120 | /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), |
| 121 | /* ITCH_SPI_D2 */ /* GPP_D21 */ |
| 122 | /* ITCH_SPI_D3 */ /* GPP_D22 */ |
| 123 | /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), |
| 124 | /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), |
| 125 | /* SATAXPCIE1 */ /* GPP_E1 */ |
| 126 | /* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), |
| 127 | /* CPU_GP0 */ /* GPP_E3 */ |
| 128 | /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), |
| 129 | /* SATA_DEVSLP1 */ /* GPP_E5 */ |
| 130 | /* SATA_DEVSLP2 */ /* GPP_E6 */ |
| 131 | /* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), |
| 132 | /* SATALED# */ /* GPP_E8 */ |
| 133 | /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), |
| 134 | /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), |
| 135 | /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), |
| 136 | /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), |
| 137 | /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), |
| 138 | /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 139 | /* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), |
| 140 | /* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), |
| 141 | /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), |
| 142 | /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), |
| 143 | /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), |
| 144 | /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), |
| 145 | /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), |
| 146 | /* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP), |
| 147 | /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), |
| 148 | /* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), |
| 149 | /* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), |
| 150 | /* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), |
| 151 | /* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), |
| 152 | /* I2C2_SDA */ /* GPP_F4 */ |
| 153 | /* I2C2_SCL */ /* GPP_F5 */ |
| 154 | /* I2C3_SDA */ /* GPP_F6 */ |
| 155 | /* I2C3_SCL */ /* GPP_F7 */ |
| 156 | /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), |
| 157 | /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), |
| 158 | /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), |
| 159 | /* I2C5_SCL */ /* GPP_F11 */ |
| 160 | /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), |
| 161 | /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), |
| 162 | /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), |
| 163 | /* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), |
| 164 | /* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), |
| 165 | /* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), |
| 166 | /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), |
| 167 | /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |
| 168 | /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), |
| 169 | /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), |
| 170 | /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), |
| 171 | /* GPP_F23 */ |
| 172 | /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), |
| 173 | /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), |
| 174 | /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), |
| 175 | /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), |
| 176 | /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), |
| 177 | /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), |
| 178 | /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), |
| 179 | /* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), |
| 180 | /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), |
| 181 | /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |
| 182 | /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), |
| 183 | /* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), |
| 184 | /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), |
| 185 | /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), |
| 186 | /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), |
| 187 | /* GPD7 */ |
| 188 | /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 189 | /* PCH_SLP_WLAN# */ /* GPD9 */ |
| 190 | /* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), |
| 191 | /* LANPHYC */ /* GPD11 */ |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 192 | }; |
Wenkai Du | 1105fad | 2015-08-21 13:11:00 -0700 | [diff] [blame^] | 193 | |
| 194 | /* Early pad configuration in romstage. */ |
| 195 | static const struct pad_config early_gpio_table[] = { |
| 196 | /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ |
| 197 | /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ |
| 198 | }; |
| 199 | |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 200 | #endif |