| Marc Jones | 3b0a626 | 2015-09-15 23:05:00 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #include <types.h> |
| 22 | #include <string.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <console/console.h> |
| 28 | #include <pc80/mc146818rtc.h> |
| 29 | #include <arch/acpi.h> |
| 30 | #include <arch/io.h> |
| 31 | #include <boot/coreboot_tables.h> |
| 32 | #include <southbridge/intel/fsp_i89xx/pch.h> |
| 33 | |
| 34 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
| 35 | void mainboard_suspend_resume(void) |
| 36 | { |
| 37 | /* Call SMM finalize() handlers before resume */ |
| 38 | outb(0xcb, 0xb2); |
| 39 | } |
| 40 | #endif |
| 41 | |
| 42 | |
| 43 | |
| 44 | // mainboard_enable is executed as first thing after |
| 45 | // enumerate_buses(). |
| 46 | |
| 47 | static void mainboard_enable(device_t dev) |
| 48 | { |
| 49 | } |
| 50 | |
| 51 | |
| 52 | |
| 53 | struct chip_operations mainboard_ops = { |
| 54 | .enable_dev = mainboard_enable, |
| 55 | }; |