Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <arch/asm.h> |
| 22 | |
Aaron Durbin | 1c65129 | 2014-08-27 12:50:26 -0500 | [diff] [blame] | 23 | #if CONFIG_ARM64_CPUS_START_IN_EL3 |
| 24 | #define SCTLR_ELx sctlr_el3 |
| 25 | #elif CONFIG_ARM64_CPUS_START_IN_EL2 |
| 26 | #define SCTLR_ELx sctlr_el2 |
| 27 | #elif CONFIG_ARM64_CPUS_START_IN_EL1 |
| 28 | #define SCTLR_ELx sctlr_el1 |
| 29 | #else |
| 30 | #error Need to know what ELx processor starts up in. |
| 31 | #endif |
| 32 | |
Aaron Durbin | a5c7f66 | 2014-08-27 14:45:59 -0500 | [diff] [blame] | 33 | #define STACK_SZ CONFIG_STACK_SIZE |
| 34 | #define EXCEPTION_STACK_SZ CONFIG_STACK_SIZE |
| 35 | |
| 36 | /* |
| 37 | * The stacks for each of the armv8 cores grows down from _estack. It is sized |
| 38 | * according to MAX_CPUS. Additionally provide exception stacks for each CPU. |
| 39 | */ |
| 40 | .section .bss, "aw", @nobits |
| 41 | .global _stack |
| 42 | .global _estack |
| 43 | .balign STACK_SZ |
| 44 | _stack: |
| 45 | .space CONFIG_MAX_CPUS*STACK_SZ |
| 46 | _estack: |
| 47 | |
| 48 | .global _stack_exceptions |
| 49 | .global _estack_exceptions |
| 50 | .balign EXCEPTION_STACK_SZ |
| 51 | _stack_exceptions: |
| 52 | .space CONFIG_MAX_CPUS*EXCEPTION_STACK_SZ |
| 53 | _estack_exceptions: |
| 54 | |
| 55 | ENTRY(cpu_get_stack) |
| 56 | mov x1, #STACK_SZ |
| 57 | mul x0, x0, x1 |
| 58 | ldr x1, 1f |
| 59 | sub x0, x1, x0 |
| 60 | ret |
| 61 | .align 3 |
| 62 | 1: |
| 63 | .quad _estack |
| 64 | ENDPROC(cpu_get_stack) |
| 65 | |
| 66 | ENTRY(cpu_get_exception_stack) |
| 67 | mov x1, #EXCEPTION_STACK_SZ |
| 68 | mul x0, x0, x1 |
| 69 | ldr x1, 1f |
| 70 | sub x0, x1, x0 |
| 71 | ret |
| 72 | .align 3 |
| 73 | 1: |
| 74 | .quad _estack_exceptions |
| 75 | ENDPROC(cpu_get_exception_stack) |
| 76 | |
Aaron Durbin | 1c65129 | 2014-08-27 12:50:26 -0500 | [diff] [blame] | 77 | /* |
| 78 | * Boot strap the processor into a C environemnt. That consists of providing |
| 79 | * 16-byte aligned stack. The programming enviroment uses SP_EL0 as its main |
| 80 | * stack while keeping SP_ELx reserved for exception entry. |
| 81 | */ |
| 82 | ENTRY(arm64_c_environment) |
Aaron Durbin | a5c7f66 | 2014-08-27 14:45:59 -0500 | [diff] [blame] | 83 | bl smp_processor_id /* x0 = cpu */ |
| 84 | mov x24, x0 |
| 85 | |
| 86 | |
| 87 | /* Set the exception stack for this cpu. */ |
| 88 | bl cpu_get_exception_stack |
Furquan Shaikh | 1af7b5d | 2014-08-21 12:52:06 -0700 | [diff] [blame] | 89 | msr SPSel, #1 |
| 90 | isb |
Furquan Shaikh | 1af7b5d | 2014-08-21 12:52:06 -0700 | [diff] [blame] | 91 | mov sp, x0 |
| 92 | |
Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 93 | /* Have stack pointer use SP_EL0. */ |
| 94 | msr SPSel, #0 |
| 95 | isb |
| 96 | |
Aaron Durbin | a5c7f66 | 2014-08-27 14:45:59 -0500 | [diff] [blame] | 97 | /* Set stack for this cpu. */ |
| 98 | mov x0, x24 /* x0 = cpu */ |
| 99 | bl cpu_get_stack |
Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 100 | mov sp, x0 |
Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 101 | |
Aaron Durbin | 3a0013d | 2014-08-27 15:52:01 -0500 | [diff] [blame^] | 102 | /* Get entry point by dereferencing c_entry. */ |
| 103 | ldr x0, 1f |
| 104 | ldr x0, [x0] |
| 105 | br x0 |
| 106 | .align 3 |
| 107 | 1: |
| 108 | .quad c_entry |
Aaron Durbin | 1c65129 | 2014-08-27 12:50:26 -0500 | [diff] [blame] | 109 | ENDPROC(arm64_c_environment) |
| 110 | |
| 111 | CPU_RESET_ENTRY(arm64_cpu_startup) |
| 112 | mrs x0, SCTLR_ELx |
| 113 | bic x0, x0, #(1 << 25) /* Little Endian */ |
| 114 | bic x0, x0, #(1 << 19) /* XN not enforced */ |
| 115 | bic x0, x0, #(1 << 12) /* Disable Instruction Cache */ |
| 116 | bic x0, x0, #0xf /* Clear SA, C, A, and M */ |
| 117 | msr SCTLR_ELx, x0 |
| 118 | isb |
| 119 | b arm64_c_environment |
| 120 | ENDPROC(arm64_cpu_startup) |
Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 121 | |
| 122 | ENTRY(stage_entry) |
Aaron Durbin | 1c65129 | 2014-08-27 12:50:26 -0500 | [diff] [blame] | 123 | b arm64_cpu_startup |
Aaron Durbin | 0df877a | 2014-07-10 12:40:30 -0500 | [diff] [blame] | 124 | ENDPROC(stage_entry) |