Angel Pons | 3157068 | 2021-02-19 20:48:50 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/x86/msr.h> |
| 6 | #include <fsp/util.h> |
| 7 | #include <intelblocks/cpulib.h> |
| 8 | #include <soc/iomap.h> |
| 9 | #include <soc/msr.h> |
| 10 | #include <soc/pci_devs.h> |
| 11 | #include <soc/romstage.h> |
| 12 | #include <soc/soc_chip.h> |
| 13 | |
| 14 | static void cpu_flex_override(FSP_M_CONFIG *m_cfg) |
| 15 | { |
| 16 | msr_t flex_ratio; |
| 17 | m_cfg->CpuRatioOverride = 1; |
| 18 | /* |
| 19 | * Set cpuratio to that value set in bootblock, This will ensure FSPM |
| 20 | * knows the intended flex ratio. |
| 21 | */ |
| 22 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 23 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
| 24 | } |
| 25 | |
| 26 | static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, |
| 27 | FSP_M_TEST_CONFIG *m_t_cfg, |
| 28 | const struct soc_intel_skylake_config *config) |
| 29 | { |
| 30 | const struct device *dev; |
| 31 | /* |
| 32 | * To enable or disable the corresponding PEG root port you need to |
| 33 | * add to the devicetree.cb: |
| 34 | * |
| 35 | * device pci 01.0 on end # enable PEG0 root port |
| 36 | * device pci 01.1 off end # do not configure PEG1 |
| 37 | * |
| 38 | * If PEG port is not defined in the device tree, it will be disabled |
| 39 | * in FSP |
| 40 | */ |
| 41 | dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ |
| 42 | m_cfg->Peg0Enable = dev && dev->enabled; |
| 43 | if (m_cfg->Peg0Enable) { |
| 44 | m_cfg->Peg0Enable = 2; |
| 45 | m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; |
| 46 | /* Use maximum possible link speed */ |
| 47 | m_cfg->Peg0MaxLinkSpeed = 0; |
| 48 | /* Power down unused lanes based on the max possible width */ |
| 49 | m_cfg->Peg0PowerDownUnusedLanes = 1; |
| 50 | /* Set [Auto] for options to enable equalization methods */ |
| 51 | m_t_cfg->Peg0Gen3EqPh2Enable = 2; |
| 52 | m_t_cfg->Peg0Gen3EqPh3Method = 0; |
| 53 | } |
| 54 | |
| 55 | dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ |
| 56 | m_cfg->Peg1Enable = dev && dev->enabled; |
| 57 | if (m_cfg->Peg1Enable) { |
| 58 | m_cfg->Peg1Enable = 2; |
| 59 | m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; |
| 60 | m_cfg->Peg1MaxLinkSpeed = 0; |
| 61 | m_cfg->Peg1PowerDownUnusedLanes = 1; |
| 62 | m_t_cfg->Peg1Gen3EqPh2Enable = 2; |
| 63 | m_t_cfg->Peg1Gen3EqPh3Method = 0; |
| 64 | } |
| 65 | |
| 66 | dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ |
| 67 | m_cfg->Peg2Enable = dev && dev->enabled; |
| 68 | if (m_cfg->Peg2Enable) { |
| 69 | m_cfg->Peg2Enable = 2; |
| 70 | m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; |
| 71 | m_cfg->Peg2MaxLinkSpeed = 0; |
| 72 | m_cfg->Peg2PowerDownUnusedLanes = 1; |
| 73 | m_t_cfg->Peg2Gen3EqPh2Enable = 2; |
| 74 | m_t_cfg->Peg2Gen3EqPh3Method = 0; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 79 | const struct soc_intel_skylake_config *config) |
| 80 | { |
| 81 | int i; |
| 82 | uint32_t mask = 0; |
| 83 | |
| 84 | m_cfg->MmioSize = 0x800; /* 2GB in MB */ |
| 85 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 86 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 87 | m_cfg->ProbelessTrace = 0; |
| 88 | m_cfg->SaGv = config->SaGv; |
| 89 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
| 90 | m_cfg->RMT = config->Rmt; |
| 91 | m_cfg->CmdTriStateDis = config->CmdTriStateDis; |
| 92 | m_cfg->DdrFreqLimit = 0; |
| 93 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
| 94 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
| 95 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 96 | if (config->PcieRpEnable[i]) |
| 97 | mask |= (1<<i); |
| 98 | } |
| 99 | m_cfg->PcieRpEnableMask = mask; |
| 100 | |
| 101 | cpu_flex_override(m_cfg); |
| 102 | |
| 103 | /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ |
| 104 | m_cfg->PchHpetBdfValid = 0; |
| 105 | |
| 106 | m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); |
| 107 | } |
| 108 | |
| 109 | static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, |
| 110 | const struct soc_intel_skylake_config *config) |
| 111 | { |
| 112 | const struct device *dev; |
| 113 | |
| 114 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Angel Pons | 3993d38 | 2021-04-05 11:40:11 +0200 | [diff] [blame^] | 115 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; |
Angel Pons | 3157068 | 2021-02-19 20:48:50 +0100 | [diff] [blame] | 116 | |
| 117 | /* |
| 118 | * If iGPU is enabled, set IGD stolen size to 64MB. The FBC |
| 119 | * hardware for skylake does not have access to the bios |
| 120 | * reserved range so it always assumes 8MB is used and so the |
| 121 | * kernel will avoid the last 8MB of the stolen window. With |
| 122 | * the default stolen size of 32MB(-8MB) there is not enough |
| 123 | * space for FBC to work with a high resolution panel. |
| 124 | * |
| 125 | * If disabled, don't reserve memory for it. |
| 126 | */ |
| 127 | m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0; |
| 128 | |
| 129 | m_cfg->PrimaryDisplay = config->PrimaryDisplay; |
| 130 | } |
| 131 | |
| 132 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 133 | { |
| 134 | const struct soc_intel_skylake_config *config; |
| 135 | const struct device *dev; |
| 136 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 137 | FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; |
| 138 | |
| 139 | config = config_of_soc(); |
| 140 | |
| 141 | soc_memory_init_params(m_cfg, config); |
| 142 | soc_peg_init_params(m_cfg, m_t_cfg, config); |
| 143 | |
| 144 | /* Skip creating Management Engine MBP HOB */ |
| 145 | m_t_cfg->SkipMbpHob = 0x01; |
| 146 | |
| 147 | /* Enable DMI Virtual Channel for ME */ |
| 148 | m_t_cfg->DmiVcm = 0x01; |
| 149 | |
| 150 | /* Enable Sending DID to ME */ |
| 151 | m_t_cfg->SendDidMsg = 0x01; |
| 152 | m_t_cfg->DidInitStat = 0x01; |
| 153 | |
| 154 | /* DCI and TraceHub configs */ |
| 155 | m_t_cfg->PchDciEn = config->PchDciEn; |
| 156 | |
| 157 | dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); |
| 158 | m_cfg->EnableTraceHub = dev && dev->enabled; |
| 159 | m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; |
| 160 | m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; |
| 161 | |
| 162 | /* Enable SMBus controller */ |
| 163 | dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); |
| 164 | m_cfg->SmbusEnable = dev && dev->enabled; |
| 165 | |
| 166 | /* Set primary graphic device */ |
| 167 | soc_primary_gfx_config_params(m_cfg, config); |
| 168 | m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; |
| 169 | |
| 170 | mainboard_memory_init_params(mupd); |
| 171 | } |
| 172 | |
| 173 | void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, |
| 174 | struct mma_config_param *mma_cfg) |
| 175 | { |
| 176 | /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ |
| 177 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
| 178 | |
| 179 | memory_cfg->MmaTestContentPtr = |
| 180 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); |
| 181 | memory_cfg->MmaTestContentSize = |
| 182 | region_device_sz(&mma_cfg->test_content); |
| 183 | memory_cfg->MmaTestConfigPtr = |
| 184 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); |
| 185 | memory_cfg->MmaTestConfigSize = |
| 186 | region_device_sz(&mma_cfg->test_param); |
| 187 | memory_cfg->MrcFastBoot = 0x00; |
| 188 | memory_cfg->SaGv = 0x02; |
| 189 | } |