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Angel Ponsf4702c22020-04-03 01:22:49 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01002
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01003#include <cpu/x86/smm.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02004#include <device/pci_ops.h>
Arthur Heymans548f33a2018-05-15 16:34:50 +02005#include <southbridge/intel/common/pmutil.h>
Angel Pons95de2312020-02-17 13:08:53 +01006#include <northbridge/intel/ironlake/ironlake.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01007#include <ec/acpi/ec.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01008
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01009void mainboard_smi_gpi(u32 gpi_sts)
10{
11}
12
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010013int mainboard_smi_apmc(u8 data)
14{
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010015 u8 tmp;
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010016 switch (data) {
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010017 case APM_CNT_ACPI_ENABLE:
18 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
19 tmp &= ~0x03;
20 tmp |= 0x02;
21 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
22 break;
23 case APM_CNT_ACPI_DISABLE:
24 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
25 tmp &= ~0x03;
26 tmp |= 0x01;
27 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
28 break;
29 default:
30 break;
31 }
32 return 0;
33}