Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/byteorder.h> |
| 26 | #include <arch/io.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 31 | #include <arch/acpi.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 32 | #include <cbmem.h> |
| 33 | #include <console/console.h> |
| 34 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 35 | #include "northbridge/intel/sandybridge/raminit.h" |
| 36 | #include "southbridge/intel/bd82x6x/pch.h" |
| 37 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 38 | #include <arch/cpu.h> |
| 39 | #include <cpu/x86/bist.h> |
| 40 | #include <cpu/x86/msr.h> |
| 41 | #include "gpio.h" |
| 42 | #if CONFIG_CHROMEOS |
| 43 | #include <vendorcode/google/chromeos/chromeos.h> |
| 44 | #endif |
| 45 | #include <cbfs.h> |
| 46 | |
| 47 | static void pch_enable_lpc(void) |
| 48 | { |
| 49 | /* EC Decode Range Port60/64 and Port62/66 */ |
| 50 | /* Enable EC and PS/2 Keyboard/Mouse*/ |
| 51 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); |
| 52 | |
| 53 | /* EC Decode Range Port68/6C */ |
| 54 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001); |
| 55 | |
| 56 | /* EC Decode Range Port 380-387 */ |
| 57 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001); |
| 58 | |
| 59 | } |
| 60 | |
| 61 | static void rcba_config(void) |
| 62 | { |
| 63 | u32 reg32; |
| 64 | |
| 65 | /* |
| 66 | * GFX INTA -> PIRQA (MSI) |
| 67 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 68 | * D28IP_P2IP ETH0 INTB -> PIRQF |
| 69 | * D28IP_P3IP SDCARD INTC -> PIRQD |
| 70 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 71 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 72 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 73 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 74 | * D31IP_TTIP THRT INTC -> PIRQA |
| 75 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 76 | * |
| 77 | * Trackpad interrupt is edge triggered and cannot be shared. |
| 78 | * TRACKPAD -> PIRQG |
| 79 | |
| 80 | */ |
| 81 | |
| 82 | /* Device interrupt pin register (board specific) */ |
| 83 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 84 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 85 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 86 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| 87 | (INTC << D28IP_P3IP); |
| 88 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 89 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 90 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 91 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 92 | |
| 93 | /* Device interrupt route registers */ |
| 94 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 95 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 96 | DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| 97 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 98 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 99 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 100 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 101 | |
| 102 | /* Enable IOAPIC (generic) */ |
| 103 | RCBA16(OIC) = 0x0100; |
| 104 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 105 | (void) RCBA16(OIC); |
| 106 | |
| 107 | /* Disable unused devices (board specific) */ |
| 108 | reg32 = RCBA32(FD); |
| 109 | reg32 |= PCH_DISABLE_ALWAYS; |
| 110 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 111 | reg32 |= PCH_DISABLE_P2P; |
| 112 | RCBA32(FD) = reg32; |
| 113 | } |
| 114 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 115 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 116 | void main(unsigned long bist) |
| 117 | { |
| 118 | int boot_mode = 0; |
| 119 | int cbmem_was_initted; |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 120 | |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 121 | struct pei_data pei_data = { |
Edward O'Callaghan | 38b9854 | 2014-10-29 06:15:57 +1100 | [diff] [blame^] | 122 | .pei_version = PEI_VERSION, |
| 123 | .mchbar = DEFAULT_MCHBAR, |
| 124 | .dmibar = DEFAULT_DMIBAR, |
| 125 | .epbar = DEFAULT_EPBAR, |
| 126 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 127 | .smbusbar = SMBUS_IO_BASE, |
| 128 | .wdbbar = 0x4000000, |
| 129 | .wdbsize = 0x1000, |
| 130 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 131 | .rcba = DEFAULT_RCBABASE, |
| 132 | .pmbase = DEFAULT_PMBASE, |
| 133 | .gpiobase = DEFAULT_GPIOBASE, |
| 134 | .thermalbase = 0xfed08000, |
| 135 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 136 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 137 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 138 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 139 | .ec_present = 1, |
| 140 | .ddr3lv_support = 0, |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 141 | // 0 = leave channel enabled |
| 142 | // 1 = disable dimm 0 on channel |
| 143 | // 2 = disable dimm 1 on channel |
| 144 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 38b9854 | 2014-10-29 06:15:57 +1100 | [diff] [blame^] | 145 | .dimm_channel0_disabled = 2, |
| 146 | .dimm_channel1_disabled = 2, |
| 147 | .max_ddr3_freq = 1600, |
| 148 | .usb_port_config = { |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 149 | /* enabled usb oc pin length */ |
| 150 | { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ |
| 151 | { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ |
| 152 | { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ |
| 153 | { 0, 0, 0x0000 }, /* P3: Empty */ |
| 154 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 155 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 156 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 157 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 158 | { 0, 4, 0x0000 }, /* P8: Empty */ |
| 159 | { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ |
| 160 | { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ |
| 161 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 162 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 163 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 164 | }, |
Edward O'Callaghan | 38b9854 | 2014-10-29 06:15:57 +1100 | [diff] [blame^] | 165 | .ddr_refresh_rate_config = 2, /* Force double refresh rate */ |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 166 | }; |
| 167 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 168 | timestamp_init(get_initial_timestamp()); |
| 169 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 170 | |
| 171 | if (bist == 0) |
| 172 | enable_lapic(); |
| 173 | |
| 174 | pch_enable_lpc(); |
| 175 | |
| 176 | /* Enable GPIOs */ |
| 177 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 178 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 179 | setup_pch_gpios(&butterfly_gpio_map); |
| 180 | |
| 181 | /* Initialize console device(s) */ |
| 182 | console_init(); |
| 183 | |
| 184 | /* Halt if there was a built in self test failure */ |
| 185 | report_bist_failure(bist); |
| 186 | |
| 187 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 188 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 189 | boot_mode = 1; |
| 190 | |
| 191 | /* System is not happy after keyboard reset... */ |
| 192 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 193 | outb(0x6, 0xcf9); |
| 194 | hlt(); |
| 195 | } |
| 196 | |
| 197 | /* Perform some early chipset initialization required |
| 198 | * before RAM initialization can work |
| 199 | */ |
| 200 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 201 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 202 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 203 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 204 | |
| 205 | post_code(0x38); |
| 206 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 207 | enable_smbus(); |
| 208 | |
| 209 | /* Prepare USB controller early in S3 resume */ |
| 210 | if (boot_mode == 2) |
| 211 | enable_usb_bar(); |
| 212 | |
| 213 | post_code(0x39); |
| 214 | |
| 215 | post_code(0x3a); |
| 216 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 217 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 218 | sdram_initialize(&pei_data); |
| 219 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 220 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 221 | post_code(0x3c); |
| 222 | |
| 223 | rcba_config(); |
| 224 | post_code(0x3d); |
| 225 | |
| 226 | quick_ram_check(); |
| 227 | post_code(0x3e); |
| 228 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 229 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 230 | if (boot_mode!=2) |
| 231 | save_mrc_data(&pei_data); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 232 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 233 | if (boot_mode==2 && !cbmem_was_initted) { |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 234 | /* Failed S3 resume, reset to come up cleanly */ |
| 235 | outb(0x6, 0xcf9); |
| 236 | hlt(); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 237 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 238 | northbridge_romstage_finalize(boot_mode==2); |
| 239 | |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 240 | post_code(0x3f); |
| 241 | #if CONFIG_CHROMEOS |
| 242 | init_chromeos(boot_mode); |
| 243 | #endif |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 244 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 245 | } |