Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
| 21 | #include <arch/io.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <cbfs.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 28 | #include <cbmem.h> |
| 29 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 30 | #include <bootmode.h> |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 31 | #include <tpm.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 33 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | 0a07c5c | 2016-02-10 03:01:37 +0100 | [diff] [blame] | 34 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 36 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 37 | #include <arch/cpu.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 38 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 39 | #include <halt.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 40 | #include "option_table.h" |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 41 | #if CONFIG_DRIVERS_UART_8250IO |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 42 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 43 | #endif |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 44 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 45 | void pch_enable_lpc(void) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 46 | { |
| 47 | /* Set COM1/COM2 decode range */ |
| 48 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 49 | |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 50 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 51 | /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ |
| 52 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 53 | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 54 | |
| 55 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 56 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 57 | |
| 58 | try_enabling_LPC47N207_uart(); |
| 59 | #else |
| 60 | /* Enable SuperIO + EC + KBC */ |
| 61 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 62 | KBC_LPC_EN); |
| 63 | #endif |
| 64 | } |
| 65 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 66 | void rcba_config(void) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 67 | { |
| 68 | u32 reg32; |
| 69 | |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 70 | /* |
| 71 | * GFX INTA -> PIRQA (MSI) |
| 72 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 73 | * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) |
| 74 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 75 | * D26IP_E2P EHCI2 INTA -> PIRQB |
| 76 | * D31IP_SIP SATA INTA -> PIRQA (MSI) |
| 77 | * D31IP_SMIP SMBUS INTC -> PIRQH |
| 78 | * D31IP_TTIP THRT INTB -> PIRQG |
| 79 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 80 | * |
| 81 | * LIGHTSENSOR -> PIRQE (Edge Triggered) |
| 82 | * TRACKPAD -> PIRQF (Edge Triggered) |
| 83 | */ |
| 84 | |
| 85 | /* Device interrupt pin register (board specific) */ |
| 86 | RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 87 | (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 88 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 89 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 90 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 91 | (INTB << D28IP_P4IP); |
| 92 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 93 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 94 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 95 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 96 | |
| 97 | /* Device interrupt route registers */ |
| 98 | DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); |
| 99 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); |
| 100 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 101 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 102 | DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); |
| 103 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 104 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 105 | |
| 106 | /* Enable IOAPIC (generic) */ |
| 107 | RCBA16(OIC) = 0x0100; |
| 108 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 109 | (void) RCBA16(OIC); |
| 110 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 111 | /* Disable unused devices (board specific) */ |
| 112 | reg32 = RCBA32(FD); |
| 113 | reg32 |= PCH_DISABLE_ALWAYS; |
| 114 | RCBA32(FD) = reg32; |
| 115 | } |
| 116 | |
Vladimir Serbinenko | 0a07c5c | 2016-02-10 03:01:37 +0100 | [diff] [blame] | 117 | static const uint8_t *locate_spd(void) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 118 | { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 119 | typedef const uint8_t spd_blob[256]; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 120 | spd_blob *spd_data; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 121 | size_t spd_file_len; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 122 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 123 | u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38); |
| 124 | u8 gpio33, gpio41, gpio49; |
| 125 | gpio33 = (gp_lvl2 >> (33-32)) & 1; |
| 126 | gpio41 = (gp_lvl2 >> (41-32)) & 1; |
| 127 | gpio49 = (gp_lvl2 >> (49-32)) & 1; |
| 128 | printk(BIOS_DEBUG, "Memory Straps:\n"); |
| 129 | printk(BIOS_DEBUG, " - memory capacity %dGB\n", |
| 130 | gpio33 ? 2 : 1); |
| 131 | printk(BIOS_DEBUG, " - die revision %d\n", |
| 132 | gpio41 ? 2 : 1); |
| 133 | printk(BIOS_DEBUG, " - vendor %s\n", |
| 134 | gpio49 ? "Samsung" : "Other"); |
| 135 | |
| 136 | int spd_index = 0; |
| 137 | |
| 138 | switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) { |
| 139 | case 0: // Other 1G Rev 1 |
| 140 | spd_index = 0; |
| 141 | break; |
| 142 | case 2: // Other 1G Rev 2 |
| 143 | spd_index = 1; |
| 144 | break; |
| 145 | case 1: // Other 2G Rev 1 |
| 146 | case 3: // Other 2G Rev 2 |
| 147 | spd_index = 2; |
| 148 | break; |
| 149 | case 4: // Samsung 1G Rev 1 |
| 150 | spd_index = 3; |
| 151 | break; |
| 152 | case 6: // Samsung 1G Rev 2 |
| 153 | spd_index = 4; |
| 154 | break; |
| 155 | case 5: // Samsung 2G Rev 1 |
| 156 | case 7: // Samsung 2G Rev 2 |
| 157 | spd_index = 5; |
| 158 | break; |
| 159 | } |
| 160 | |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 161 | spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 162 | &spd_file_len); |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 163 | if (!spd_data) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 164 | die("SPD data not found."); |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 165 | if (spd_file_len < (spd_index + 1) * 256) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 166 | die("Missing SPD data."); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 167 | // leave onboard dimm address at f0, and copy spd data there. |
Vladimir Serbinenko | 0a07c5c | 2016-02-10 03:01:37 +0100 | [diff] [blame] | 168 | return spd_data[spd_index]; |
| 169 | } |
| 170 | |
| 171 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 172 | { |
| 173 | struct pei_data pei_data_template = { |
| 174 | .pei_version = PEI_VERSION, |
| 175 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 176 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 177 | .epbar = DEFAULT_EPBAR, |
| 178 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 179 | .smbusbar = SMBUS_IO_BASE, |
| 180 | .wdbbar = 0x4000000, |
| 181 | .wdbsize = 0x1000, |
| 182 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 183 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
| 184 | .pmbase = DEFAULT_PMBASE, |
| 185 | .gpiobase = DEFAULT_GPIOBASE, |
| 186 | .thermalbase = 0xfed08000, |
| 187 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 188 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 189 | .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, |
| 190 | .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, |
| 191 | .ec_present = 1, |
| 192 | // 0 = leave channel enabled |
| 193 | // 1 = disable dimm 0 on channel |
| 194 | // 2 = disable dimm 1 on channel |
| 195 | // 3 = disable dimm 0+1 on channel |
| 196 | .dimm_channel0_disabled = 2, |
| 197 | .dimm_channel1_disabled = 2, |
| 198 | .max_ddr3_freq = 1333, |
| 199 | .usb_port_config = { |
| 200 | { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ |
| 201 | { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ |
| 202 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 203 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 204 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 205 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 206 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 207 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 208 | { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ |
| 209 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 210 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 211 | { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ |
| 212 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 213 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 214 | }, |
| 215 | }; |
| 216 | *pei_data = pei_data_template; |
| 217 | // leave onboard dimm address at f0, and copy spd data there. |
| 218 | memcpy(pei_data->spd_data[0], locate_spd(), 256); |
| 219 | } |
| 220 | |
| 221 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 222 | /* enabled power usb oc pin */ |
| 223 | { 1, 1, 0 }, /* P0: Port 0 (OC0) */ |
| 224 | { 1, 1, 1 }, /* P1: Port 1 (OC1) */ |
| 225 | { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ |
| 226 | { 1, 0, -1 }, /* P3: MMC (no OC) */ |
| 227 | { 0, 0, -1 }, /* P4: Empty */ |
| 228 | { 0, 0, -1 }, /* P5: Empty */ |
| 229 | { 0, 0, -1 }, /* P6: Empty */ |
| 230 | { 0, 0, -1 }, /* P7: Empty */ |
| 231 | { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ |
| 232 | { 0, 0, -1 }, /* P9: Empty */ |
| 233 | { 0, 0, -1 }, /* P10: Empty */ |
| 234 | { 1, 0, -1 }, /* P11: Camera (no OC) */ |
| 235 | { 0, 0, -1 }, /* P12: Empty */ |
| 236 | { 0, 0, -1 }, /* P13: Empty */ |
| 237 | }; |
| 238 | |
| 239 | void mainboard_get_spd(spd_raw_data *spd) |
| 240 | { |
Patrick Rudolph | 2585209 | 2016-04-07 18:51:12 +0200 | [diff] [blame] | 241 | /* get onboard dimm spd */ |
| 242 | memcpy(&spd[0], locate_spd(), 256); |
| 243 | /* read removable dimm spd */ |
| 244 | read_spd(&spd[2], 0x50); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 245 | } |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 246 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 247 | void mainboard_early_init(int s3resume) |
| 248 | { |
| 249 | init_bootmode_straps(); |
| 250 | } |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 251 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 252 | int mainboard_should_reset_usb(int s3resume) |
| 253 | { |
| 254 | return !s3resume; |
| 255 | } |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 256 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 257 | void mainboard_config_superio(void) |
| 258 | { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 259 | } |