Tristan Corrick | 3f7de06 | 2018-03-02 03:02:07 +1300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017–2018 Tristan Corrick <tristan@corrick.kiwi> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame^] | 17 | #include <device/pnp_ops.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Tristan Corrick | 3f7de06 | 2018-03-02 03:02:07 +1300 | [diff] [blame] | 19 | #include <device/dram/ddr3.h> |
| 20 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 21 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 22 | #include <southbridge/intel/bd82x6x/pch.h> |
| 23 | #include <superio/nuvoton/common/nuvoton.h> |
| 24 | #include <superio/nuvoton/nct6776/nct6776.h> |
| 25 | |
| 26 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 27 | { 1, 0, 0 }, |
| 28 | { 1, 0, 0 }, |
| 29 | { 1, 0, 1 }, |
| 30 | { 1, 0, 1 }, |
| 31 | { 1, 0, 2 }, |
| 32 | { 1, 0, 2 }, |
| 33 | { 1, 0, 3 }, |
| 34 | { 1, 0, 3 }, |
| 35 | { 1, 0, 4 }, |
| 36 | { 1, 0, 4 }, |
| 37 | { 1, 0, 5 }, |
| 38 | { 1, 0, 5 }, |
| 39 | { 1, 0, 6 }, |
| 40 | { 1, 0, 6 }, |
| 41 | }; |
| 42 | |
| 43 | void pch_enable_lpc(void) |
| 44 | { |
| 45 | pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); |
| 46 | } |
| 47 | |
| 48 | void mainboard_rcba_config(void) |
| 49 | { |
| 50 | } |
| 51 | |
| 52 | void mainboard_early_init(int s3resume) |
| 53 | { |
| 54 | } |
| 55 | |
| 56 | void mainboard_config_superio(void) |
| 57 | { |
| 58 | static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); |
| 59 | static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); |
| 60 | |
| 61 | nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); |
| 62 | |
| 63 | /* Select HWM/LED functions instead of floppy functions. */ |
| 64 | pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); |
| 65 | pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); |
| 66 | |
| 67 | /* Power RAM in S3. */ |
| 68 | pnp_set_logical_device(ACPI_DEV); |
| 69 | pnp_write_config(ACPI_DEV, 0xe4, 0x10); |
| 70 | |
| 71 | nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); |
| 72 | } |
| 73 | |
| 74 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 75 | { |
| 76 | read_spd(&spd[0], 0x50, id_only); |
| 77 | read_spd(&spd[1], 0x51, id_only); |
| 78 | read_spd(&spd[2], 0x52, id_only); |
| 79 | read_spd(&spd[3], 0x53, id_only); |
| 80 | } |