Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 23 | #include <rules.h> |
| 24 | #include <device/pci_def.h> |
Aaron Durbin | c2b7779 | 2016-07-14 00:26:50 -0500 | [diff] [blame] | 25 | #include <halt.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 26 | #include <soc/iomap.h> |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 28 | #include <soc/pm.h> |
| 29 | #include <device/device.h> |
| 30 | #include <device/pci.h> |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 31 | #include <vboot/vboot_common.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 32 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 33 | static uintptr_t read_pmc_mmio_bar(void) |
| 34 | { |
| 35 | uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); |
| 36 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 37 | } |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 38 | |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 39 | uintptr_t get_pmc_mmio_bar(void) |
| 40 | { |
| 41 | return read_pmc_mmio_bar(); |
| 42 | } |
| 43 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 44 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 45 | const char * const bit_names[]) |
| 46 | { |
| 47 | int i; |
| 48 | |
| 49 | if (!status) |
| 50 | return; |
| 51 | |
| 52 | for (i = num_bits - 1; i >= 0; i--) { |
| 53 | if (status & (1 << i)) { |
| 54 | if (bit_names[i]) |
| 55 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 56 | else |
| 57 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 58 | } |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 63 | { |
| 64 | static const char * const smi_sts_bits[] = { |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 65 | [BIOS_SMI_STS] = "BIOS", |
| 66 | [LEGACY_USB_SMI_STS] = "LEGACY USB", |
| 67 | [SLP_SMI_STS] = "SLP_SMI", |
| 68 | [APM_SMI_STS] = "APM", |
| 69 | [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 70 | [FAKE_PM1_SMI_STS] = "PM1", |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 71 | [GPIO_SMI_STS]= "GPIO_SMI", |
| 72 | [GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI", |
| 73 | [MC_SMI_STS] = "MCSMI", |
| 74 | [TCO_SMI_STS] = "TCO", |
| 75 | [PERIODIC_SMI_STS] = "PERIODIC", |
| 76 | [SERIRQ_SMI_STS] = "SERIRQ", |
| 77 | [SMBUS_SMI_STS] = "SMBUS_SMI", |
| 78 | [XHCI_SMI_STS] = "XHCI", |
| 79 | [HSMBUS_SMI_STS] = "HOST_SMBUS", |
| 80 | [SCS_SMI_STS] = "SCS", |
| 81 | [PCIE_SMI_STS] = "PCI_EXP_SMI", |
| 82 | [SCC2_SMI_STS] = "SCC2", |
| 83 | [SPI_SSMI_STS] = "SPI_SSMI", |
| 84 | [SPI_SMI_STS] = "SPI", |
| 85 | [PMC_OCP_SMI_STS] = "OCP_CSE", |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | if (!smi_sts) |
| 89 | return 0; |
| 90 | |
| 91 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 92 | print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); |
| 93 | printk(BIOS_DEBUG, "\n"); |
| 94 | |
| 95 | return smi_sts; |
| 96 | } |
| 97 | |
| 98 | static uint32_t reset_smi_status(void) |
| 99 | { |
| 100 | uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); |
| 101 | outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); |
| 102 | return smi_sts; |
| 103 | } |
| 104 | |
| 105 | uint32_t clear_smi_status(void) |
| 106 | { |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 107 | uint32_t sts = reset_smi_status(); |
| 108 | |
| 109 | /* |
| 110 | * Check for power button status if nothing else is indicating an SMI |
| 111 | * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status |
| 112 | * bit in the SMI status register. That makes things difficult for |
| 113 | * determining if the power button caused an SMI. |
| 114 | */ |
| 115 | if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) { |
| 116 | uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 117 | |
| 118 | /* Fake PM1 status bit if power button pressed. */ |
| 119 | if (pm1_sts & PWRBTN_STS) |
| 120 | sts |= (1 << FAKE_PM1_SMI_STS); |
| 121 | } |
| 122 | |
| 123 | return print_smi_status(sts); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | uint32_t get_smi_en(void) |
| 127 | { |
| 128 | return inl(ACPI_PMIO_BASE + SMI_EN); |
| 129 | } |
| 130 | |
| 131 | void enable_smi(uint32_t mask) |
| 132 | { |
| 133 | uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); |
| 134 | smi_en |= mask; |
| 135 | outl(smi_en, ACPI_PMIO_BASE + SMI_EN); |
| 136 | } |
| 137 | |
| 138 | void disable_smi(uint32_t mask) |
| 139 | { |
| 140 | uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); |
| 141 | smi_en &= ~mask; |
| 142 | outl(smi_en, ACPI_PMIO_BASE + SMI_EN); |
| 143 | } |
| 144 | |
| 145 | void enable_pm1_control(uint32_t mask) |
| 146 | { |
| 147 | uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 148 | pm1_cnt |= mask; |
| 149 | outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); |
| 150 | } |
| 151 | |
| 152 | void disable_pm1_control(uint32_t mask) |
| 153 | { |
| 154 | uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 155 | pm1_cnt &= ~mask; |
| 156 | outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); |
| 157 | } |
| 158 | |
| 159 | static uint16_t reset_pm1_status(void) |
| 160 | { |
| 161 | uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 162 | outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); |
| 163 | return pm1_sts; |
| 164 | } |
| 165 | |
| 166 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 167 | { |
| 168 | static const char * const pm1_sts_bits[] = { |
| 169 | [0] = "TMROF", |
| 170 | [5] = "GBL", |
| 171 | [8] = "PWRBTN", |
| 172 | [10] = "RTC", |
| 173 | [11] = "PRBTNOR", |
| 174 | [13] = "USB", |
| 175 | [14] = "PCIEXPWAK", |
| 176 | [15] = "WAK", |
| 177 | }; |
| 178 | |
| 179 | if (!pm1_sts) |
| 180 | return 0; |
| 181 | |
| 182 | printk(BIOS_SPEW, "PM1_STS: "); |
| 183 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 184 | printk(BIOS_SPEW, "\n"); |
| 185 | |
| 186 | return pm1_sts; |
| 187 | } |
| 188 | |
| 189 | uint16_t clear_pm1_status(void) |
| 190 | { |
| 191 | return print_pm1_status(reset_pm1_status()); |
| 192 | } |
| 193 | |
| 194 | void enable_pm1(uint16_t events) |
| 195 | { |
| 196 | outw(events, ACPI_PMIO_BASE + PM1_EN); |
| 197 | } |
| 198 | |
| 199 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 200 | { |
| 201 | static const char * const tco_sts_bits[] = { |
| 202 | [3] = "TIMEOUT", |
| 203 | [17] = "SECOND_TO", |
| 204 | }; |
| 205 | |
| 206 | if (!tco_sts) |
| 207 | return 0; |
| 208 | |
| 209 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 210 | print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); |
| 211 | printk(BIOS_DEBUG, "\n"); |
| 212 | |
| 213 | return tco_sts; |
| 214 | } |
| 215 | |
| 216 | static uint32_t reset_tco_status(void) |
| 217 | { |
| 218 | uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); |
| 219 | uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); |
| 220 | |
| 221 | outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); |
| 222 | return tco_sts & tco_en; |
| 223 | } |
| 224 | |
| 225 | uint32_t clear_tco_status(void) |
| 226 | { |
| 227 | return print_tco_status(reset_tco_status()); |
| 228 | } |
| 229 | |
| 230 | void enable_gpe(uint32_t mask) |
| 231 | { |
| 232 | uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); |
| 233 | gpe0a_en |= mask; |
| 234 | outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); |
| 235 | } |
| 236 | |
| 237 | void disable_gpe(uint32_t mask) |
| 238 | { |
| 239 | uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); |
| 240 | gpe0a_en &= ~mask; |
| 241 | outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); |
| 242 | } |
| 243 | |
| 244 | void disable_all_gpe(void) |
| 245 | { |
| 246 | disable_gpe(~0); |
| 247 | } |
| 248 | |
| 249 | |
| 250 | static uint32_t reset_gpe_status(void) |
| 251 | { |
| 252 | uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); |
| 253 | outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); |
| 254 | return gpe_sts; |
| 255 | } |
| 256 | |
| 257 | static uint32_t print_gpe_sts(uint32_t gpe_sts) |
| 258 | { |
| 259 | static const char * const gpe_sts_bits[] = { |
| 260 | [0] = "PCIE_SCI", |
| 261 | [2] = "SWGPE", |
| 262 | [3] = "PCIE_WAKE0", |
| 263 | [4] = "PUNIT", |
| 264 | [6] = "PCIE_WAKE1", |
| 265 | [7] = "PCIE_WAKE2", |
| 266 | [8] = "PCIE_WAKE3", |
| 267 | [9] = "PCI_EXP", |
| 268 | [10] = "BATLOW", |
| 269 | [11] = "CSE_PME", |
| 270 | [12] = "XDCI_PME", |
| 271 | [13] = "XHCI_PME", |
| 272 | [14] = "AVS_PME", |
| 273 | [15] = "GPIO_TIER1_SCI", |
| 274 | [16] = "SMB_WAK", |
| 275 | [17] = "SATA_PME", |
| 276 | }; |
| 277 | |
| 278 | if (!gpe_sts) |
| 279 | return gpe_sts; |
| 280 | |
| 281 | printk(BIOS_DEBUG, "GPE0a_STS: "); |
| 282 | print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); |
| 283 | printk(BIOS_DEBUG, "\n"); |
| 284 | |
| 285 | return gpe_sts; |
| 286 | } |
| 287 | |
| 288 | uint32_t clear_gpe_status(void) |
| 289 | { |
| 290 | return print_gpe_sts(reset_gpe_status()); |
| 291 | } |
| 292 | |
| 293 | void clear_pmc_status(void) |
| 294 | { |
| 295 | uint32_t prsts; |
| 296 | uint32_t gen_pmcon1; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 297 | uintptr_t pmc_bar0 = read_pmc_mmio_bar(); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 298 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 299 | prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 300 | gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 301 | |
| 302 | /* Clear the status bits. The RPS field is cleared on a 0 write. */ |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 303 | write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS); |
| 304 | write32((void *)(pmc_bar0 + PRSTS), prsts); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | |
| 308 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 309 | int chipset_prev_sleep_state(struct chipset_power_state *ps) |
| 310 | { |
| 311 | /* Default to S0. */ |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 312 | int prev_sleep_state = ACPI_S0; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 313 | |
| 314 | if (ps->pm1_sts & WAK_STS) { |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 315 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 316 | case ACPI_S3: |
| 317 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) |
| 318 | prev_sleep_state = ACPI_S3; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 319 | break; |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 320 | case ACPI_S5: |
| 321 | prev_sleep_state = ACPI_S5; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 322 | break; |
| 323 | } |
Hannah Williams | 5992afa | 2016-06-23 09:50:28 -0700 | [diff] [blame] | 324 | |
| 325 | /* Clear SLP_TYP. */ |
| 326 | outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 327 | } |
| 328 | return prev_sleep_state; |
| 329 | } |
| 330 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 331 | /* |
| 332 | * This function re-writes the gpe0 register values in power state |
| 333 | * cbmem variable. After system wakes from sleep state internal PMC logic |
| 334 | * writes default values in GPE_CFG register which gives a wrong offset to |
| 335 | * calculate the wake reason. So we need to set it again to the routing |
| 336 | * table as per the devicetree. |
| 337 | */ |
| 338 | void fixup_power_state(void) |
| 339 | { |
| 340 | int i; |
| 341 | struct chipset_power_state *ps; |
| 342 | |
| 343 | ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 344 | if (ps == NULL) |
| 345 | return; |
| 346 | |
| 347 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 348 | ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); |
| 349 | ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); |
| 350 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 351 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 352 | } |
| 353 | } |
| 354 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 355 | /* returns prev_sleep_state */ |
| 356 | int fill_power_state(struct chipset_power_state *ps) |
| 357 | { |
| 358 | int i; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 359 | uintptr_t pmc_bar0 = read_pmc_mmio_bar(); |
| 360 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 361 | ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 362 | ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); |
| 363 | ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 364 | ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 365 | ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 366 | ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1)); |
| 367 | ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); |
| 368 | ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 369 | |
| 370 | ps->prev_sleep_state = chipset_prev_sleep_state(ps); |
| 371 | |
| 372 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 373 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 374 | printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n", |
| 375 | ps->prsts, ps->tco_sts); |
| 376 | printk(BIOS_DEBUG, |
| 377 | "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 378 | ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |
| 379 | printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", |
| 380 | inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); |
| 381 | for (i=0; i < GPE0_REG_MAX; i++) { |
| 382 | ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); |
| 383 | ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); |
| 384 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 385 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 386 | } |
| 387 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 388 | return ps->prev_sleep_state; |
| 389 | } |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 390 | |
| 391 | int vboot_platform_is_resuming(void) |
| 392 | { |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 393 | if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) |
| 394 | return 0; |
| 395 | |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 396 | return acpi_sleep_from_pm1(inl(ACPI_PMIO_BASE + PM1_CNT)) == ACPI_S3; |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 397 | } |
Andrey Petrov | 0f593c2 | 2016-06-17 15:30:13 -0700 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * If possible, lock 0xcf9. Once the register is locked, it can't be changed. |
| 401 | * This lock is reset on cold boot, hard reset, soft reset and Sx. |
| 402 | */ |
| 403 | void global_reset_lock(void) |
| 404 | { |
| 405 | uintptr_t etr = read_pmc_mmio_bar() + ETR; |
| 406 | uint32_t reg; |
| 407 | |
| 408 | reg = read32((void *)etr); |
| 409 | if (reg & CF9_LOCK) |
| 410 | return; |
| 411 | reg |= CF9_LOCK; |
| 412 | write32((void *)etr, reg); |
| 413 | } |
| 414 | |
| 415 | /* |
| 416 | * Enable or disable global reset. If global reset is enabled, hard reset and |
| 417 | * soft reset will trigger global reset, where both host and TXE are reset. |
| 418 | * This is cleared on cold boot, hard reset, soft reset and Sx. |
| 419 | */ |
| 420 | void global_reset_enable(bool enable) |
| 421 | { |
| 422 | uintptr_t etr = read_pmc_mmio_bar() + ETR; |
| 423 | uint32_t reg; |
| 424 | |
| 425 | reg = read32((void *)etr); |
| 426 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
| 427 | write32((void *)etr, reg); |
| 428 | } |
Furquan Shaikh | 4c1cb42 | 2016-06-23 14:00:05 -0700 | [diff] [blame] | 429 | |
| 430 | /* |
| 431 | * The PM1 control is set to S5 when vboot requests a reboot because the power |
| 432 | * state code above may not have collected its data yet. Therefore, set it to |
| 433 | * S5 when vboot requests a reboot. That's necessary if vboot fails in the |
| 434 | * resume path and requests a reboot. This prevents a reboot loop where the |
| 435 | * error is continually hit on the failing vboot resume path. |
| 436 | */ |
| 437 | void vboot_platform_prepare_reboot(void) |
| 438 | { |
| 439 | const uint16_t port = ACPI_PMIO_BASE + PM1_CNT; |
| 440 | outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); |
| 441 | } |
Aaron Durbin | c2b7779 | 2016-07-14 00:26:50 -0500 | [diff] [blame] | 442 | |
| 443 | void poweroff(void) |
| 444 | { |
| 445 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 446 | halt(); |
| 447 | } |