Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 18 | #include <device/mmio.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <delay.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 24 | #include <device/pci_ops.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 25 | #include <drivers/intel/gma/edid.h> |
| 26 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 27 | #include <drivers/intel/gma/intel_bios.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame] | 28 | #include <drivers/intel/gma/libgfxinit.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 29 | #include <pc80/vga.h> |
| 30 | #include <pc80/vga_io.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 31 | #include <southbridge/intel/ibexpeak/nvs.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 32 | #include <drivers/intel/gma/opregion.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 33 | #include <cbmem.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 34 | #include <types.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 35 | |
| 36 | #include "chip.h" |
| 37 | #include "nehalem.h" |
| 38 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 39 | /* some vga option roms are used for several chipsets but they only have one |
| 40 | * PCI ID in their header. If we encounter such an option rom, we need to do |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 41 | * the mapping ourselves |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 42 | */ |
| 43 | |
| 44 | u32 map_oprom_vendev(u32 vendev) |
| 45 | { |
| 46 | u32 new_vendev = vendev; |
| 47 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 48 | /* none currently. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 49 | |
| 50 | return new_vendev; |
| 51 | } |
| 52 | |
| 53 | static struct resource *gtt_res = NULL; |
| 54 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 55 | u32 gtt_read(u32 reg) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 56 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | return read32(res2mmio(gtt_res, reg, 0)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 58 | } |
| 59 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 60 | void gtt_write(u32 reg, u32 data) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 61 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 62 | write32(res2mmio(gtt_res, reg, 0), data); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 65 | #define GTT_RETRY 1000 |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 66 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 67 | { |
| 68 | unsigned try = GTT_RETRY; |
| 69 | u32 data; |
| 70 | |
| 71 | while (try--) { |
| 72 | data = gtt_read(reg); |
| 73 | if ((data & mask) == value) |
| 74 | return 1; |
| 75 | udelay(10); |
| 76 | } |
| 77 | |
| 78 | printk(BIOS_ERR, "GT init timeout\n"); |
| 79 | return 0; |
| 80 | } |
| 81 | |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 82 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 83 | { |
| 84 | const global_nvs_t *gnvs_ptr = gnvs; |
| 85 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 86 | } |
| 87 | |
| 88 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 89 | { |
| 90 | global_nvs_t *gnvs_ptr = gnvs; |
| 91 | if (gnvs_ptr) |
| 92 | gnvs_ptr->aslb = aslb; |
| 93 | } |
| 94 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 95 | static void gma_pm_init_post_vbios(struct device *dev) |
| 96 | { |
| 97 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
| 98 | u32 reg32; |
| 99 | |
| 100 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 101 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 102 | /* Setup Digital Port Hotplug */ |
| 103 | reg32 = gtt_read(0xc4030); |
| 104 | if (!reg32) { |
| 105 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 106 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 107 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 108 | gtt_write(0xc4030, reg32); |
| 109 | } |
| 110 | |
| 111 | /* Setup Panel Power On Delays */ |
| 112 | reg32 = gtt_read(0xc7208); |
| 113 | if (!reg32) { |
| 114 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 115 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 116 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 117 | gtt_write(0xc7208, reg32); |
| 118 | } |
| 119 | |
| 120 | /* Setup Panel Power Off Delays */ |
| 121 | reg32 = gtt_read(0xc720c); |
| 122 | if (!reg32) { |
| 123 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 124 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 125 | gtt_write(0xc720c, reg32); |
| 126 | } |
| 127 | |
| 128 | /* Setup Panel Power Cycle Delay */ |
| 129 | if (conf->gpu_panel_power_cycle_delay) { |
| 130 | reg32 = gtt_read(0xc7210); |
| 131 | reg32 &= ~0xff; |
| 132 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 133 | gtt_write(0xc7210, reg32); |
| 134 | } |
| 135 | |
| 136 | /* Enable Backlight if needed */ |
| 137 | if (conf->gpu_cpu_backlight) { |
| 138 | gtt_write(0x48250, (1 << 31)); |
| 139 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 140 | } |
| 141 | if (conf->gpu_pch_backlight) { |
| 142 | gtt_write(0xc8250, (1 << 31)); |
| 143 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 144 | } |
| 145 | } |
| 146 | |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 147 | /* Enable SCI to ACPI _GPE._L06 */ |
| 148 | static void gma_enable_swsci(void) |
| 149 | { |
| 150 | u16 reg16; |
| 151 | |
| 152 | /* clear DMISCI status */ |
| 153 | reg16 = inw(DEFAULT_PMBASE + TCO1_STS); |
| 154 | reg16 &= DMISCI_STS; |
| 155 | outw(DEFAULT_PMBASE + TCO1_STS, reg16); |
| 156 | |
| 157 | /* clear acpi tco status */ |
| 158 | outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); |
| 159 | |
| 160 | /* enable acpi tco scis */ |
| 161 | reg16 = inw(DEFAULT_PMBASE + GPE0_EN); |
| 162 | reg16 |= TCOSCI_EN; |
| 163 | outw(DEFAULT_PMBASE + GPE0_EN, reg16); |
| 164 | } |
| 165 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 166 | static void gma_func0_init(struct device *dev) |
| 167 | { |
| 168 | u32 reg32; |
| 169 | |
| 170 | /* IGD needs to be Bus Master */ |
| 171 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 172 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 173 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 174 | |
Arthur Heymans | f266dc6 | 2019-10-01 22:02:31 +0200 | [diff] [blame] | 175 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 176 | if (!gtt_res || !gtt_res->base) |
| 177 | return; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 178 | |
Arthur Heymans | 38750f8 | 2019-10-03 09:34:57 +0200 | [diff] [blame] | 179 | if (!acpi_is_wakeup_s3() && |
| 180 | CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 181 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 182 | int lightup_ok; |
| 183 | printk(BIOS_SPEW, "Initializing VGA without OPROM."); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 184 | |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 185 | gma_gfxinit(&lightup_ok); |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 186 | /* Linux relies on VBT for panel info. */ |
| 187 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 188 | "$VBT IRONLAKE-MOBILE"); |
| 189 | } else { |
| 190 | /* PCI Init, will run VBIOS */ |
| 191 | pci_dev_init(dev); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 192 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 193 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 194 | /* Post VBIOS init */ |
| 195 | gma_pm_init_post_vbios(dev); |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 196 | |
| 197 | gma_enable_swsci(); |
| 198 | intel_gma_restore_opregion(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 199 | } |
| 200 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 201 | static void gma_read_resources(struct device *dev) |
| 202 | { |
| 203 | pci_dev_read_resources(dev); |
| 204 | |
| 205 | struct resource *res; |
| 206 | |
| 207 | /* Set the graphics memory to write combining. */ |
| 208 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 209 | if (res == NULL) { |
| 210 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 211 | return; |
| 212 | } |
| 213 | res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 214 | pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001); |
| 215 | pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 216 | res->base = (resource_t) 0xd0000000; |
| 217 | res->size = (resource_t) 0x10000000; |
| 218 | } |
| 219 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 220 | const struct i915_gpu_controller_info * |
| 221 | intel_gma_get_controller_info(void) |
| 222 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 223 | struct device *dev = pcidev_on_root(0x2, 0); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 224 | if (!dev) { |
| 225 | return NULL; |
| 226 | } |
| 227 | struct northbridge_intel_nehalem_config *chip = dev->chip_info; |
| 228 | return &chip->gfx; |
| 229 | } |
| 230 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 231 | static void gma_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 232 | { |
| 233 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 234 | if (!gfx) { |
| 235 | return; |
| 236 | } |
| 237 | |
| 238 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 239 | } |
| 240 | |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 241 | static unsigned long |
| 242 | gma_write_acpi_tables(struct device *const dev, |
| 243 | unsigned long current, |
| 244 | struct acpi_rsdp *const rsdp) |
| 245 | { |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 246 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 247 | global_nvs_t *gnvs; |
| 248 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 249 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 250 | return current; |
| 251 | |
| 252 | current += sizeof(igd_opregion_t); |
| 253 | |
| 254 | /* GNVS has been already set up */ |
| 255 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 256 | if (gnvs) { |
| 257 | /* IGD OpRegion Base Address */ |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 258 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 259 | } else { |
| 260 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 261 | } |
| 262 | |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 263 | current = acpi_align_current(current); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 264 | return current; |
| 265 | } |
| 266 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 267 | static struct pci_operations gma_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 268 | .set_subsystem = pci_dev_set_subsystem, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 269 | }; |
| 270 | |
| 271 | static struct device_operations gma_func0_ops = { |
| 272 | .read_resources = gma_read_resources, |
| 273 | .set_resources = pci_dev_set_resources, |
| 274 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 275 | .acpi_fill_ssdt_generator = gma_ssdt, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 276 | .init = gma_func0_init, |
| 277 | .scan_bus = 0, |
| 278 | .enable = 0, |
| 279 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 280 | .write_acpi_tables = gma_write_acpi_tables, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 281 | }; |
| 282 | |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 283 | static const unsigned short pci_device_ids[] = { |
| 284 | 0x0046, 0x0102, 0x0106, 0x010a, 0x0112, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 285 | 0x0116, 0x0122, 0x0126, 0x0156, |
| 286 | 0x0166, |
| 287 | 0 |
| 288 | }; |
| 289 | |
| 290 | static const struct pci_driver gma __pci_driver = { |
| 291 | .ops = &gma_func0_ops, |
| 292 | .vendor = PCI_VENDOR_ID_INTEL, |
| 293 | .devices = pci_device_ids, |
| 294 | }; |