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Bruce Griffith27ed80b2014-08-15 11:46:25 -06001#
2# This file is part of the coreboot project.
3#
Bruce Griffith27ed80b2014-08-15 11:46:25 -06004#
5# This program is free software; you can redistribute it and/or modify
6# it under the terms of the GNU General Public License as published by
7# the Free Software Foundation; version 2 of the License.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
Bruce Griffith27ed80b2014-08-15 11:46:25 -060014
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030015config NORTHBRIDGE_AMD_PI
Martin Roth595e7772015-04-26 18:53:26 -060016 bool
Marc Jones21cde8b2017-05-07 16:47:36 -060017 default y if CPU_AMD_PI
Marc Jones21cde8b2017-05-07 16:47:36 -060018 default n
Kyösti Mälkki6e37b0a2017-04-17 06:45:56 +030019 select CBMEM_TOP_BACKUP
Bruce Griffith27ed80b2014-08-15 11:46:25 -060020
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030021if NORTHBRIDGE_AMD_PI
22
Ricardo Ribalda Delgadoa1328922016-12-28 15:16:22 +010023config BOTTOMIO_POSITION
24 hex "Bottom of 32-bit IO space"
25 default 0xD0000000
26 help
27 If PCI peripherals with big BARs are connected to the system
28 the bottom of the IO must be decreased to allocate such
29 devices.
30
31 Declare the beginning of the 128MB-aligned MMIO region. This
32 option is useful when PCI peripherals requesting large address
33 ranges are present.
34
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030035config CONSOLE_VGA_MULTI
36 bool
37 default n
38
39config S3_VGA_ROM_RUN
40 bool
41 default n
42
Patrick Georgi0bb83462019-11-22 20:58:58 +010043source "src/northbridge/amd/pi/00630F01/Kconfig"
44source "src/northbridge/amd/pi/00730F01/Kconfig"
45source "src/northbridge/amd/pi/00660F01/Kconfig"
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030046
WANG Siyuan2dcd0fc2015-06-02 16:25:58 +080047config HW_MEM_HOLE_SIZEK
48 hex
49 default 0x200000
50
WANG Siyuan2dcd0fc2015-06-02 16:25:58 +080051config HEAP_SIZE
52 hex
53 default 0xc0000
54
Michał Żygowskie7192882019-11-23 19:02:19 +010055config NUM_OF_IOAPICS
56 int
57 default 3
58
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030059endif # NORTHBRIDGE_AMD_PI