src/mainboard/google/brya/variants/glassway/overridetree.cb

fw_config
	field THERMAL_SOLUTION 0
		option THERMAL_SOLUTION_PASSIVE  0
		option THERMAL_SOLUTION_ACTIVE   1
	end
	field DB_USB 5 7
		option DB_NONE			 0
		option DB_1C			 1
		option DB_1A			 2
		option DB_1C_1A			 3
	end
	field SD_CARD 8
		option SD_ABSENT		 0
		option SD_GL9750S		 1
	end
	field WIFI_SAR_ID 10 12
		option WIFI_SAR_ID_0		 0
	end
	field TOUCHSCREEN_SOURCE 32 33
		option TOUCHSCREEN_UNPROVISIONED 0
		option TOUCHSCREEN_ELAN0001      1
		option TOUCHSCREEN_GTCH7503      2
	end
end

chip soc/intel/alderlake
	register "sagv" = "SaGv_Enabled"

	# EMMC Tx CMD Delay
	# Refer to EDS-Vol2-42.3.7.
	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

	# EMMC TX DATA Delay 1
	# Refer to EDS-Vol2-42.3.8.
	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"

	# EMMC TX DATA Delay 2
	# Refer to EDS-Vol2-42.3.9.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"

	# EMMC RX CMD/DATA Delay 1
	# Refer to EDS-Vol2-42.3.10.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"

	# EMMC RX CMD/DATA Delay 2
	# Refer to EDS-Vol2-42.3.12.
	# [17:16] stands for Rx Clock before Output Buffer,
	#         00: Rx clock after output buffer,
	#         01: Rx clock before output buffer,
	#         10: Automatic selection based on working mode.
	#         11: Reserved
	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10048"

	# EMMC Rx Strobe Delay
	# Refer to EDS-Vol2-42.3.11.
	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

	# SOC Aux orientation override:
	# This is a bitfield that corresponds to up to 4 TCSS ports.
	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
	# TcssAuxOri = 0101b
	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
	# motherboard to USBC connector
	register "tcss_aux_ori" = "5"

	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN

	# Configure external V1P05/Vnn/VnnSx Rails
	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 1,
		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
		.v1p05_voltage_mv = 1050,
		.vnn_voltage_mv = 780,
		.vnn_sx_voltage_mv = 1050,
		.v1p05_icc_max_ma = 500,
		.vnn_icc_max_ma = 500,
	}"

	# Enable the Cnvi BT Audio Offload
	register "cnvi_bt_audio_offload" = "1"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| I2C0              | TPM. Early init is        |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#| I2C1              | Touchscreen               |
	#| I2C2              | Sub-board(PSensor)/WCAM   |
	#| I2C3              | Audio                     |
	#| I2C5              | Trackpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.i2c[0] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST_PLUS,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST_PLUS,
				.scl_lcnt = 55,
				.scl_hcnt = 30,
				.sda_hold = 7,
			}
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 157,
				.scl_hcnt = 79,
				.sda_hold = 40,
			}
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 157,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 40,
			}
		},
	}"

	device domain 0 on
		device ref dtt on
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""Memory""
				register "options.tsr[1].desc" = ""Charger""
				register "options.tsr[2].desc" = ""Ambient""

				# TODO: below values are initial reference values only
				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 3000,
							.max_power = 6000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 200
						},
					.pl2 = {
							.min_power = 25000,
							.max_power = 25000,
							.time_window_min = 1,
							.time_window_max = 1,
							.granularity = 1000
						}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 1700 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				device generic 0 on
					probe THERMAL_SOLUTION THERMAL_SOLUTION_PASSIVE
				end
			end
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""Memory""
				register "options.tsr[1].desc" = ""Charger""
				register "options.tsr[2].desc" = ""Ambient""

				# TODO: below values are initial reference values only
				## Active Policy
				register "policies.active" = "{
					[0] = {
						.target = DPTF_CPU,
						.thresholds = {
								TEMP_PCT(85, 90),
								TEMP_PCT(80, 80),
								TEMP_PCT(75, 70),
								TEMP_PCT(70, 50),
								TEMP_PCT(65, 30),
						}
					},
					[1] = {
						.target = DPTF_TEMP_SENSOR_2,
						.thresholds = {
								TEMP_PCT(50, 90),
								TEMP_PCT(48, 70),
								TEMP_PCT(46, 60),
								TEMP_PCT(43, 40),
								TEMP_PCT(40, 30),
						}
					}
				}"

				# TODO: below values are initial reference values only
				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 12000,
							.max_power = 15000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 200
						},
					.pl2 = {
							.min_power = 35000,
							.max_power = 35000,
							.time_window_min = 1,
							.time_window_max = 1,
							.granularity = 1000
						}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 1700 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				## Fan Performance Control (Percent, Speed, Noise, Power)
				register "controls.fan_perf" = "{
					[0] = { 100, 6000, 220, 2200, },
					[1] = {  92, 5500, 180, 1800, },
					[2] = {  85, 5000, 145, 1450, },
					[3] = {  70, 4400, 115, 1150, },
					[4] = {  56, 3900,  90,  900, },
					[5] = {  45, 3300,  55,  550, },
					[6] = {  38, 3000,  30,  300, },
					[7] = {  33, 2900,  15,  150, },
					[8] = {  10,  800,  10,  100, },
					[9] = {   0,    0,   0,   50, }
				}"

				## Fan options
				register "options.fan.fine_grained_control" = "1"
				register "options.fan.step_size" = "2"

				device generic 1 on
					probe THERMAL_SOLUTION THERMAL_SOLUTION_ACTIVE
				end
			end
		end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "enable_cnvi_ddr_rfim" = "true"
				device generic 0 on end
			end
		end
		device ref i2c1 on
			chip drivers/i2c/generic
				register "hid" = ""ELAN0001""
				register "desc" = ""ELAN Touchscreen""
				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
				register "reset_delay_ms" = "20"
				register "reset_off_delay_ms" = "4"
				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
				register "stop_delay_ms" = "5"
				register "stop_off_delay_ms" = "25"
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
				register "enable_delay_ms" = "25"
				register "has_power_resource" = "1"
				device i2c 10 on
					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_UNPROVISIONED
					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN0001
				end
			end

			chip drivers/i2c/hid
				register "generic.hid" = ""GTCH7503""
				register "generic.desc" = ""G2TOUCH Touchscreen""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
				register "generic.reset_delay_ms" = "50"
				register "generic.reset_off_delay_ms" = "5"
				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
				register "generic.stop_delay_ms" = "30"
				register "generic.stop_off_delay_ms" = "10"
				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
				register "generic.enable_delay_ms" = "5"
				register "generic.has_power_resource" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 40  on
					probe TOUCHSCREEN_SOURCE TOUCHSCREEN_GTCH7503
				end
			end
		end #I2C1
		device ref i2c3 on
			chip drivers/i2c/generic
				register "hid" = ""RTL5682""
				register "name" = ""RT58""
				register "desc" = ""Headset Codec""
				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
				# Set the jd_src to RT5668_JD1 for jack detection
				register "property_count" = "1"
				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
				register "property_list[0].name" = ""realtek,jd-src""
				register "property_list[0].integer" = "1"
				device i2c 1a on end
			end
			chip drivers/generic/alc1015
				register "hid" = ""RTL1019""
				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
				device generic 1 on end
			end
		end #I2C3
		device ref i2c5 on
			chip drivers/i2c/generic
				register "hid" = ""ELAN0000""
				register "desc" = ""ELAN Touchpad""
				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
				register "wake" = "GPE0_DW2_14"
				register "detect" = "1"
				device i2c 15 on end
			end
			chip drivers/i2c/hid
				register "generic.hid" = ""PNP0C50""
				register "generic.desc" = ""PIXART Touchpad""
				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
				register "generic.wake" = "GPE0_DW2_14"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2c on end
			end
		end #I2C5
		device ref pcie_rp4 on
			# Enable wlan PCIe 4 using clk 2
			register "pch_pcie_rp[PCH_RP(4)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip drivers/wifi/generic
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on end
			end
		end
		device ref pcie_rp7 on
			# Enable SD Card PCIe 7 using clk 3
			register "pch_pcie_rp[PCH_RP(7)]" = "{
				.clk_src = 3,
				.clk_req = 3,
				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
				register "srcclk_pin" = "3"
				device generic 0 on end
			end
			probe SD_CARD SD_GL9750S
		end
		device ref emmc on
			probe STORAGE STORAGE_EMMC
		end
		device ref ish on
			chip drivers/intel/ish
				register "add_acpi_dma_property" = "true"
				device generic 0 on end
			end
			probe STORAGE STORAGE_UFS
		end
		device ref ufs on
			probe STORAGE STORAGE_UFS
		end
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port2 as usb2_port
						use tcss_usb3_port2 as usb3_port
						device generic 1 alias conn1 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C1 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port2 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C1 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port4 on
							probe DB_USB DB_1C_1A
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" =
							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port8 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port2 on
							probe DB_USB DB_1C_1A
						end
					end
				end
			end
		end
	end
end