Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 18 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 20 | #include <cbmem.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 21 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 22 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 23 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 24 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 25 | #include "sandybridge.h" |
| 26 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 27 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 28 | { |
| 29 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 30 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 31 | return tom; |
| 32 | } |
| 33 | |
| 34 | void *cbmem_top(void) |
| 35 | { |
| 36 | return (void *) smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 37 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 38 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 39 | static uintptr_t northbridge_get_tseg_base(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 40 | { |
| 41 | return ALIGN_DOWN(smm_region_start(), 1*MiB); |
| 42 | } |
| 43 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 44 | static size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 45 | { |
| 46 | return CONFIG_SMM_TSEG_SIZE; |
| 47 | } |
| 48 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 49 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 50 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 51 | *start = northbridge_get_tseg_base(); |
| 52 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 53 | } |
| 54 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 55 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 56 | { |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 57 | uintptr_t top_of_ram; |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 58 | |
Kyösti Mälkki | b84c833 | 2016-12-01 10:48:43 +0200 | [diff] [blame] | 59 | top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 60 | /* Cache 8MiB below the top of ram. On sandybridge systems the top of |
| 61 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 62 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 63 | * for ramstage before setting up the entire RAM as cacheable. */ |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 64 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 65 | |
| 66 | /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems |
| 67 | * is where the TSEG region resides. However, it is not restricted |
| 68 | * to SMM mode until SMM has been relocated. By setting the region |
| 69 | * to cacheable it provides faster access when relocating the SMM |
| 70 | * handler as well as using the TSEG region for other purposes. */ |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 71 | postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 72 | } |