Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Andrew Wu <arw@dmp.com.tw> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <console/console.h> |
| 25 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 26 | #include "drivers/pc80/i8254.c" |
| 27 | #include "northbridge/dmp/vortex86ex/northbridge.h" |
| 28 | #include "southbridge/dmp/vortex86ex/southbridge.h" |
| 29 | #include "northbridge/dmp/vortex86ex/raminit.c" |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame^] | 30 | #include "cpu/dmp/dmp_post_code.h" |
Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 31 | |
| 32 | #define DMP_CPUID_SX 0x31504d44 |
| 33 | #define DMP_CPUID_DX 0x32504d44 |
| 34 | #define DMP_CPUID_MX 0x33504d44 |
| 35 | #define DMP_CPUID_DX2 0x34504d44 |
| 36 | #define DMP_CPUID_MX_PLUS 0x35504d44 |
| 37 | #define DMP_CPUID_EX 0x37504d44 |
| 38 | |
Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 39 | static u32 get_dmp_id(void) |
| 40 | { |
| 41 | return pci_read_config32(NB, NB_REG_CID); |
| 42 | } |
| 43 | |
| 44 | /* Indirect access registers for Watch-dog timer, GPIO PORT 0,1 |
| 45 | * Index port is for I/O port 22h |
| 46 | * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function |
| 47 | * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer |
| 48 | * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1 |
| 49 | */ |
| 50 | static void write_indirect_reg(u8 index, u8 data) |
| 51 | { |
| 52 | outb(index, 0x22); |
| 53 | outb(data, 0x23); |
| 54 | } |
| 55 | |
| 56 | static void lock_indirect_reg(void) |
| 57 | { |
| 58 | write_indirect_reg(0x13, 0x00); |
| 59 | } |
| 60 | |
| 61 | static void unlock_indirect_reg(void) |
| 62 | { |
| 63 | write_indirect_reg(0x13, 0xc5); |
| 64 | } |
| 65 | |
| 66 | static void disable_watchdog(void) |
| 67 | { |
| 68 | unlock_indirect_reg(); |
| 69 | // disable watchdog timer |
| 70 | write_indirect_reg(0x37, 0x0); |
| 71 | } |
| 72 | |
| 73 | void set_ex_powerdown_control(void) |
| 74 | { |
| 75 | u32 powerdown_ctrl; |
| 76 | powerdown_ctrl = pci_read_config32(SB, 0xbc); |
| 77 | #if CONFIG_TEMP_POWERDOWN |
| 78 | powerdown_ctrl |= (1 << 31); |
| 79 | #endif |
| 80 | #if CONFIG_SATA_POWERDOWN |
| 81 | powerdown_ctrl |= (1 << 30); |
| 82 | #endif |
| 83 | #if CONFIG_ADC_POWERDOWN |
| 84 | powerdown_ctrl |= (1 << 28); |
| 85 | #endif |
| 86 | #if CONFIG_PCIE0_POWERDOWN |
| 87 | powerdown_ctrl |= (1 << 13); |
| 88 | #endif |
| 89 | #if CONFIG_MAC_POWERDOWN |
| 90 | powerdown_ctrl |= (1 << 3); |
| 91 | #endif |
| 92 | #if CONFIG_USB1_POWERDOWN |
| 93 | powerdown_ctrl |= (1 << 1); |
| 94 | #endif |
| 95 | #if CONFIG_IDE_POWERDOWN |
| 96 | powerdown_ctrl |= (1 << 0); |
| 97 | #endif |
| 98 | pci_write_config32(SB, 0xbc, powerdown_ctrl); |
| 99 | } |
| 100 | |
| 101 | static void set_pci_nb_pmcr(void) |
| 102 | { |
| 103 | u8 pmcr = pci_read_config8(NB, NB_REG_PMCR); |
| 104 | /* |
| 105 | * Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks. |
| 106 | * Set PCI Master Burst Write Length (BL) to Burst length over 3. |
| 107 | */ |
| 108 | pmcr |= 0x0f; |
| 109 | pci_write_config8(NB, NB_REG_PMCR, pmcr); |
| 110 | } |
| 111 | |
| 112 | static void set_pci_sb_lpccr(void) |
| 113 | { |
| 114 | u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR); |
| 115 | /* Set PCI Soft Reset Control to 1. |
| 116 | * (When the CPU soft reset is initialized, PCIRST# will be active.) |
| 117 | * Set P92FE to 1. (I/O port 92 Register Write Function Enable.) |
| 118 | * Set P92S to 1. (Internal Port 92h Selected.) |
| 119 | */ |
| 120 | lpccr |= 0x16; |
| 121 | pci_write_config8(SB, SB_REG_LPCCR, lpccr); |
| 122 | /* enable fast ga20 */ |
| 123 | outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT); |
| 124 | } |
| 125 | |
| 126 | static u32 make_uart_config(u16 base, u8 irq) |
| 127 | { |
| 128 | /* Set base IO address only, skip IRQ. IRQ will be setup in |
| 129 | * southbridge stage. */ |
| 130 | u32 cfg = 0; |
| 131 | cfg |= 1 << 23; // UE = enabled. |
| 132 | cfg |= base; // UIOA. |
| 133 | return cfg; |
| 134 | } |
| 135 | |
| 136 | #define SETUP_UART(n) \ |
| 137 | uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\ |
| 138 | outl(uart_cfg, 0xc00 + (n - 1) * 4); |
| 139 | |
| 140 | static void ex_uart_early_init(void) |
| 141 | { |
| 142 | #if CONFIG_TTYS0_BASE |
| 143 | u32 uart_cfg = 0; |
| 144 | /* Set UART Config I/O base address to 0xc00 */ |
| 145 | pci_write_config16(SB, 0x60, 0xc01); |
| 146 | /* If serial console base address is defined, find out which |
| 147 | * UART uses this address, and setup this UART first. */ |
| 148 | #if CONFIG_TTYS0_BASE == CONFIG_UART1_IO |
| 149 | SETUP_UART(1) |
| 150 | #elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO |
| 151 | SETUP_UART(2) |
| 152 | #elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO |
| 153 | SETUP_UART(3) |
| 154 | #elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO |
| 155 | SETUP_UART(4) |
| 156 | #elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO |
| 157 | SETUP_UART(5) |
| 158 | #elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO |
| 159 | SETUP_UART(6) |
| 160 | #elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO |
| 161 | SETUP_UART(7) |
| 162 | #elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO |
| 163 | SETUP_UART(8) |
| 164 | #elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO |
| 165 | SETUP_UART(9) |
| 166 | #elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO |
| 167 | SETUP_UART(10) |
| 168 | #endif |
| 169 | #endif |
| 170 | } |
| 171 | |
| 172 | static void init_wdt1(void) |
| 173 | { |
| 174 | #if CONFIG_WDT1_INITIALIZE |
| 175 | #if CONFIG_WDT1_ENABLE |
| 176 | outb(0x1 << 6, 0xa8); |
| 177 | #endif |
| 178 | u8 wdt1_signal_reg = 0; |
| 179 | #if CONFIG_WDT1_SINGAL_NMI |
| 180 | wdt1_signal_reg = 0x0c << 4; |
| 181 | #elif CONFIG_WDT1_SIGNAL_RESET |
| 182 | wdt1_signal_reg = 0x0d << 4; |
| 183 | #elif CONFIG_WDT1_SIGNAL_SMI |
| 184 | wdt1_signal_reg = 0x0e << 4; |
| 185 | #endif |
| 186 | outb(wdt1_signal_reg, 0xa9); |
| 187 | #endif |
| 188 | } |
| 189 | |
| 190 | /* Fill 32bit pattern into specified DRAM region. */ |
| 191 | static void fill_dram(u32 * p, u32 pattern, u32 test_len) |
| 192 | { |
| 193 | if (test_len == 0) |
| 194 | return; |
| 195 | #if 0 |
| 196 | // C version, very slow. |
| 197 | for (p = (u32 *) 0; (u32) p < test_len; p++) { |
| 198 | *p = pattern; |
| 199 | } |
| 200 | #endif |
| 201 | // ASM version, much faster. |
| 202 | asm volatile ( |
| 203 | "cld\n\t" |
| 204 | "rep\n\t" |
| 205 | "stosl" |
| 206 | : /* no output registers */ |
| 207 | : "c" (test_len / 4), "a" (pattern), "D" (p) |
| 208 | ); |
| 209 | } |
| 210 | |
| 211 | /* Verify 32bit pattern in specified DRAM region. |
| 212 | * Return -1 if ok, failed memory address if error. */ |
| 213 | static int verify_dram(u32 * p, u32 pattern, u32 test_len) |
| 214 | { |
| 215 | if (test_len == 0) |
| 216 | return -1; |
| 217 | #if 0 |
| 218 | // C version, very slow. |
| 219 | for (p = (u32 *) 0; (u32) p < test_len; p++) { |
| 220 | if (*p != pattern) { |
| 221 | return (int)p; |
| 222 | } |
| 223 | } |
| 224 | return -1; |
| 225 | #endif |
| 226 | u16 flags; |
| 227 | int addr; |
| 228 | asm volatile ( |
| 229 | "cld\n\t" |
| 230 | "rep\n\t" |
| 231 | "scasl\n\t" |
| 232 | "lahf\n\t" |
| 233 | : "=a" (flags), "=D" (addr) |
| 234 | : "c" (test_len / 4), "a" (pattern), "D" (p) |
| 235 | ); |
| 236 | if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6. |
| 237 | { |
| 238 | return -1; // verify ok |
| 239 | } |
| 240 | return addr - 4; // verify error, return error address. |
| 241 | } |
| 242 | |
| 243 | static void test_dram_stability(void) |
| 244 | { |
| 245 | u32 test_len = 2048 * 1024; |
| 246 | u32 pat = 0x5aa5a55a; |
| 247 | u32 ext_mem_start = 0xc0000; |
| 248 | u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len; |
| 249 | u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0; |
| 250 | if (ext_mem_test_len > 0) { |
| 251 | /* Enable all shadow RAM region C0000 - FFFFF. */ |
| 252 | pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0); |
| 253 | } |
| 254 | int v; |
| 255 | fill_dram((u32 *) 0, pat, base_mem_test_len); |
| 256 | fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); |
| 257 | v = verify_dram((u32 *) 0, pat, base_mem_test_len); |
| 258 | if (v == -1) { |
| 259 | v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); |
| 260 | } |
| 261 | /* Change pattern and test again */ |
| 262 | if (v == -1) { |
| 263 | pat = 0xa55a5aa5; |
| 264 | fill_dram((u32 *) 0, pat, base_mem_test_len); |
| 265 | fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); |
| 266 | v = verify_dram((u32 *) 0, pat, base_mem_test_len); |
| 267 | if (v == -1) { |
| 268 | v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len); |
| 269 | } |
| 270 | } |
| 271 | if (v != -1) { |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame^] | 272 | post_code(POST_DMP_DRAM_TEST_ERR); |
Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 273 | print_emerg("DRAM stablility test error!\nADDR = "); |
| 274 | print_emerg_hex32(v); |
| 275 | print_emerg(", WRITE = "); |
| 276 | print_emerg_hex32(pat); |
| 277 | u32 r = *(u32 *) v; |
| 278 | print_emerg(", READ = "); |
| 279 | print_emerg_hex32(r); |
| 280 | print_emerg(", XOR = "); |
| 281 | print_emerg_hex32(r ^ pat); |
| 282 | print_emerg("\n"); |
| 283 | die("System halted.\n"); |
| 284 | } |
| 285 | if (ext_mem_test_len > 0) { |
| 286 | /* Disable shadow RAM. */ |
| 287 | pci_write_config32(NB, NB_REG_MAR, 0x0); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static void enable_l2_cache(void) |
| 292 | { |
| 293 | /* |
| 294 | * Enable L2 cache by setting PCI N/B function 1 L2 cache |
| 295 | * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN). |
| 296 | */ |
| 297 | u32 reg_nb_f1_e8; |
| 298 | reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8); |
| 299 | reg_nb_f1_e8 |= 3; |
| 300 | pci_write_config8(NB1, 0xe8, reg_nb_f1_e8); |
| 301 | } |
| 302 | |
| 303 | static void main(unsigned long bist) |
| 304 | { |
| 305 | device_t dev; |
| 306 | u32 dmp_id; |
| 307 | |
| 308 | dmp_id = get_dmp_id(); |
| 309 | if (dmp_id != DMP_CPUID_EX) { |
| 310 | /* Not DMP Vortex86EX CPU. */ |
| 311 | post_code(POST_DMP_ID_ERR); |
| 312 | while (1) |
| 313 | hlt(); |
| 314 | } |
| 315 | disable_watchdog(); |
| 316 | set_ex_powerdown_control(); |
| 317 | set_pci_nb_pmcr(); |
| 318 | set_pci_sb_lpccr(); |
| 319 | ex_uart_early_init(); |
| 320 | |
| 321 | console_init(); |
| 322 | |
| 323 | init_wdt1(); |
| 324 | |
| 325 | /* Initialize i8254 timers */ |
| 326 | post_code(0x42); |
| 327 | setup_i8254(); |
| 328 | |
| 329 | /* Initialize DRAM */ |
| 330 | u8 reg_nb_f1_cc; |
| 331 | /* Setup DDR3 Timing reg 0-3 / Config reg */ |
| 332 | pci_write_config16(NB, 0x6e, 0x0a2f); |
| 333 | pci_write_config32(NB, 0x74, 0x84010200); |
| 334 | pci_write_config32(NB, 0x78, 0x33405544); |
| 335 | pci_write_config32(NB, 0x7c, 0x2e0f0e0b); |
| 336 | /* Disable enhance read push write */ |
| 337 | reg_nb_f1_cc = pci_read_config8(NB1, 0xcc); |
| 338 | reg_nb_f1_cc &= ~(1 << 4); |
| 339 | pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); |
| 340 | if (detect_ddr3_dram_size()) { |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame^] | 341 | post_code(POST_DMP_DRAM_SIZING_ERR); |
Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 342 | die("DRAM sizing error!\n"); |
| 343 | } |
| 344 | /* Reset enhance read push write to default(enable) */ |
| 345 | reg_nb_f1_cc |= (1 << 4); |
| 346 | pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); |
| 347 | |
| 348 | print_ddr3_memory_setup(); |
| 349 | test_dram_stability(); |
| 350 | |
| 351 | /* CPU setup, romcc pukes on invd() */ |
| 352 | asm volatile ("invd"); |
| 353 | enable_cache(); |
| 354 | |
| 355 | enable_l2_cache(); |
| 356 | } |