Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 3 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 4 | #include <cpu/cpu.h> |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 5 | #include <cpu/intel/cpu_ids.h> |
| 6 | #include <cpu/intel/microcode.h> |
| 7 | #include <cpu/x86/msr.h> |
| 8 | #include <cpu/x86/name.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 12 | #include <soc/bootblock.h> |
| 13 | #include <soc/pci_devs.h> |
| 14 | |
| 15 | static struct { |
| 16 | u32 cpuid; |
| 17 | const char *name; |
| 18 | } cpu_table[] = { |
| 19 | { CPUID_METEORLAKE_A0_1, "MeteorLake A0" }, |
| 20 | { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, |
| 21 | }; |
| 22 | |
| 23 | static struct { |
| 24 | u16 mchid; |
| 25 | const char *name; |
| 26 | } mch_table[] = { |
| 27 | { PCI_DID_INTEL_MTL_M_ID, "MeteorLake M" }, |
| 28 | { PCI_DID_INTEL_MTL_P_ID_1, "MeteorLake P" }, |
| 29 | { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" }, |
Subrata Banik | 88f863c | 2022-06-13 20:42:44 +0530 | [diff] [blame] | 30 | { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | static struct { |
| 34 | u16 espiid; |
| 35 | const char *name; |
| 36 | } pch_table[] = { |
| 37 | { PCI_DID_INTEL_MTL_ESPI_0, "MeteorLake SOC" }, |
| 38 | { PCI_DID_INTEL_MTL_ESPI_1, "MeteorLake SOC" }, |
| 39 | { PCI_DID_INTEL_MTL_ESPI_2, "MeteorLake SOC" }, |
| 40 | { PCI_DID_INTEL_MTL_ESPI_3, "MeteorLake SOC" }, |
| 41 | { PCI_DID_INTEL_MTL_ESPI_4, "MeteorLake SOC" }, |
| 42 | { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" }, |
| 43 | { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" }, |
| 44 | { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" }, |
| 45 | }; |
| 46 | |
| 47 | static struct { |
| 48 | u16 igdid; |
| 49 | const char *name; |
| 50 | } igd_table[] = { |
| 51 | { PCI_DID_INTEL_MTL_M_GT2, "MeteorLake-M GT2" }, |
| 52 | { PCI_DID_INTEL_MTL_P_GT2_1, "MeteorLake-P GT2" }, |
| 53 | { PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" }, |
Wonkyu Kim | 25c2075 | 2022-07-04 20:43:47 -0700 | [diff] [blame] | 54 | { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, |
Ravi Sarawadi | 33005df | 2022-10-11 23:54:55 -0700 | [diff] [blame^] | 55 | { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | static inline uint8_t get_dev_revision(pci_devfn_t dev) |
| 59 | { |
| 60 | return pci_read_config8(dev, PCI_REVISION_ID); |
| 61 | } |
| 62 | |
| 63 | static inline uint16_t get_dev_id(pci_devfn_t dev) |
| 64 | { |
| 65 | return pci_read_config16(dev, PCI_DEVICE_ID); |
| 66 | } |
| 67 | |
| 68 | static void report_cpu_info(void) |
| 69 | { |
| 70 | u32 i, cpu_id, cpu_feature_flag; |
| 71 | char cpu_name[49]; |
| 72 | int vt, txt, aes; |
| 73 | static const char *const mode[] = {"NOT ", ""}; |
| 74 | const char *cpu_type = "Unknown"; |
| 75 | |
| 76 | fill_processor_name(cpu_name); |
| 77 | cpu_id = cpu_get_cpuid(); |
| 78 | |
| 79 | /* Look for string to match the name */ |
| 80 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 81 | if (cpu_table[i].cpuid == cpu_id) { |
| 82 | cpu_type = cpu_table[i].name; |
| 83 | break; |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 88 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 89 | cpu_id, cpu_type, get_current_microcode_rev()); |
| 90 | |
| 91 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 92 | aes = !!(cpu_feature_flag & CPUID_AES); |
| 93 | txt = !!(cpu_feature_flag & CPUID_SMX); |
| 94 | vt = !!(cpu_feature_flag & CPUID_VMX); |
| 95 | printk(BIOS_DEBUG, |
| 96 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 97 | mode[aes], mode[txt], mode[vt]); |
| 98 | } |
| 99 | |
| 100 | static void report_mch_info(void) |
| 101 | { |
| 102 | int i; |
| 103 | pci_devfn_t dev = PCI_DEV_ROOT; |
| 104 | uint16_t mchid = get_dev_id(dev); |
| 105 | const char *mch_type = "Unknown"; |
| 106 | |
| 107 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 108 | if (mch_table[i].mchid == mchid) { |
| 109 | mch_type = mch_table[i].name; |
| 110 | break; |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 115 | mchid, get_dev_revision(dev), mch_type); |
| 116 | } |
| 117 | |
| 118 | static void report_pch_info(void) |
| 119 | { |
| 120 | int i; |
| 121 | pci_devfn_t dev = PCI_DEV_ESPI; |
| 122 | uint16_t espiid = get_dev_id(dev); |
| 123 | const char *pch_type = "Unknown"; |
| 124 | |
| 125 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 126 | if (pch_table[i].espiid == espiid) { |
| 127 | pch_type = pch_table[i].name; |
| 128 | break; |
| 129 | } |
| 130 | } |
| 131 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 132 | espiid, get_dev_revision(dev), pch_type); |
| 133 | } |
| 134 | |
| 135 | static void report_igd_info(void) |
| 136 | { |
| 137 | int i; |
| 138 | pci_devfn_t dev = PCI_DEV_IGD; |
| 139 | uint16_t igdid = get_dev_id(dev); |
| 140 | const char *igd_type = "Unknown"; |
| 141 | |
| 142 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 143 | if (igd_table[i].igdid == igdid) { |
| 144 | igd_type = igd_table[i].name; |
| 145 | break; |
| 146 | } |
| 147 | } |
| 148 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 149 | igdid, get_dev_revision(dev), igd_type); |
| 150 | } |
| 151 | |
| 152 | void report_platform_info(void) |
| 153 | { |
| 154 | report_cpu_info(); |
| 155 | report_mch_info(); |
| 156 | report_pch_info(); |
| 157 | report_igd_info(); |
| 158 | } |