Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5639736 | 2017-09-07 22:13:10 +0300 | [diff] [blame] | 2 | |
3 | #include <gcccar.inc> | ||||
4 | #include <cpu/x86/cache.h> | ||||
5 | |||||
6 | .code32 | ||||
7 | .globl chipset_teardown_car | ||||
8 | |||||
9 | chipset_teardown_car: | ||||
10 | pop %esp | ||||
11 | |||||
12 | /* Disable cache */ | ||||
13 | movl %cr0, %eax | ||||
14 | orl $CR0_CacheDisable, %eax | ||||
15 | movl %eax, %cr0 | ||||
16 | |||||
17 | AMD_DISABLE_STACK | ||||
18 | |||||
19 | /* enable cache */ | ||||
20 | movl %cr0, %eax | ||||
21 | andl $(~(CR0_CD | CR0_NW)), %eax | ||||
22 | movl %eax, %cr0 | ||||
23 | |||||
24 | jmp *%esp |