Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the LinuxBIOS project. |
| 3 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 4 | ## Copyright (C) 2007 AMD |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 5 | ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 6 | ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> |
| 7 | ## (Thanks to LSRA University of Mannheim for their support) |
| 8 | ## |
| 9 | ## This program is free software; you can redistribute it and/or modify |
| 10 | ## it under the terms of the GNU General Public License as published by |
| 11 | ## the Free Software Foundation; either version 2 of the License, or |
| 12 | ## (at your option) any later version. |
| 13 | ## |
| 14 | ## This program is distributed in the hope that it will be useful, |
| 15 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | ## GNU General Public License for more details. |
| 18 | ## |
| 19 | ## You should have received a copy of the GNU General Public License |
| 20 | ## along with this program; if not, write to the Free Software |
| 21 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | ## |
| 23 | |
| 24 | ## |
| 25 | ## Compute the location and size of where this firmware image |
| 26 | ## (linuxBIOS plus bootloader) will live in the boot rom chip. |
| 27 | ## |
| 28 | if USE_FAILOVER_IMAGE |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 29 | default ROM_SECTION_SIZE = FAILOVER_SIZE |
| 30 | default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 31 | else |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 32 | if USE_FALLBACK_IMAGE |
| 33 | default ROM_SECTION_SIZE = FALLBACK_SIZE |
| 34 | default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) |
| 35 | else |
| 36 | default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) |
| 37 | default ROM_SECTION_OFFSET = 0 |
| 38 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 39 | end |
| 40 | |
| 41 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 42 | ## Compute the start location and size size of the LinuxBIOS bootloader. |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 43 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 44 | default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) |
| 45 | default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 46 | |
| 47 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 48 | ## Compute where this copy of LinuxBIOS will start in the boot ROM. |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 49 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 50 | default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 51 | |
| 52 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 53 | ## Compute a range of ROM that can be cached to speed up LinuxBIOS |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 54 | ## execution speed. |
| 55 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 56 | ## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 57 | ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
| 58 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 59 | default XIP_ROM_SIZE = (64 * 1024) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 60 | |
| 61 | if USE_FAILOVER_IMAGE |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 62 | default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 63 | else |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 64 | if USE_FALLBACK_IMAGE |
| 65 | default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) |
| 66 | else |
| 67 | default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) |
| 68 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 69 | end |
| 70 | |
| 71 | arch i386 end |
| 72 | |
| 73 | ## |
| 74 | ## Build the objects we have code for in this directory. |
| 75 | ## |
| 76 | |
| 77 | driver mainboard.o |
| 78 | |
| 79 | #dir /drivers/ati/ragexl |
| 80 | |
| 81 | # Needed by irq_tables and mptable and acpi_tables. |
| 82 | object get_bus_conf.o |
| 83 | |
| 84 | if HAVE_MP_TABLE |
| 85 | object mptable.o |
| 86 | end |
| 87 | |
| 88 | if HAVE_PIRQ_TABLE |
| 89 | object irq_tables.o |
| 90 | end |
| 91 | |
| 92 | if USE_DCACHE_RAM |
| 93 | if CONFIG_USE_INIT |
| 94 | makerule ./auto.o |
| 95 | depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 96 | action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" |
| 97 | end |
| 98 | else |
| 99 | makerule ./auto.inc |
| 100 | depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 101 | action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" |
| 102 | action "perl -e 's/.rodata/.rom.data/g' -pi $@" |
| 103 | action "perl -e 's/.text/.section .rom.text/g' -pi $@" |
| 104 | end |
| 105 | end |
| 106 | end |
| 107 | |
| 108 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 109 | ## Build our 16 bit and 32 bit LinuxBIOS entry code. |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 110 | ## |
| 111 | if HAVE_FAILOVER_BOOT |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 112 | if USE_FAILOVER_IMAGE |
| 113 | mainboardinit cpu/x86/16bit/entry16.inc |
| 114 | ldscript /cpu/x86/16bit/entry16.lds |
| 115 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 116 | else |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 117 | if USE_FALLBACK_IMAGE |
| 118 | mainboardinit cpu/x86/16bit/entry16.inc |
| 119 | ldscript /cpu/x86/16bit/entry16.lds |
| 120 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 121 | end |
| 122 | |
| 123 | mainboardinit cpu/x86/32bit/entry32.inc |
| 124 | |
| 125 | if USE_DCACHE_RAM |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 126 | if CONFIG_USE_INIT |
| 127 | ldscript /cpu/x86/32bit/entry32.lds |
| 128 | ldscript /cpu/amd/car/cache_as_ram.lds |
| 129 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 130 | end |
| 131 | |
| 132 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 133 | ## Build our reset vector (this is where LinuxBIOS is entered). |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 134 | ## |
| 135 | if HAVE_FAILOVER_BOOT |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 136 | if USE_FAILOVER_IMAGE |
| 137 | mainboardinit cpu/x86/16bit/reset16.inc |
| 138 | ldscript /cpu/x86/16bit/reset16.lds |
| 139 | else |
| 140 | mainboardinit cpu/x86/32bit/reset32.inc |
| 141 | ldscript /cpu/x86/32bit/reset32.lds |
| 142 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 143 | else |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 144 | if USE_FALLBACK_IMAGE |
| 145 | mainboardinit cpu/x86/16bit/reset16.inc |
| 146 | ldscript /cpu/x86/16bit/reset16.lds |
| 147 | else |
| 148 | mainboardinit cpu/x86/32bit/reset32.inc |
| 149 | ldscript /cpu/x86/32bit/reset32.lds |
| 150 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 151 | end |
| 152 | |
| 153 | if USE_DCACHE_RAM |
| 154 | else |
| 155 | ### Should this be in the northbridge code? |
| 156 | mainboardinit arch/i386/lib/cpu_reset.inc |
| 157 | end |
| 158 | |
| 159 | ## |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 160 | ## Include an ID string (for safe flashing). |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 161 | ## |
| 162 | mainboardinit southbridge/nvidia/ck804/id.inc |
| 163 | ldscript /southbridge/nvidia/ck804/id.lds |
| 164 | |
| 165 | ## |
| 166 | ## ROMSTRAP table for CK804 |
| 167 | ## |
| 168 | if HAVE_FAILOVER_BOOT |
| 169 | if USE_FAILOVER_IMAGE |
| 170 | mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| 171 | ldscript /southbridge/nvidia/ck804/romstrap.lds |
| 172 | end |
| 173 | else |
| 174 | if USE_FALLBACK_IMAGE |
| 175 | mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| 176 | ldscript /southbridge/nvidia/ck804/romstrap.lds |
| 177 | end |
| 178 | end |
| 179 | |
| 180 | if USE_DCACHE_RAM |
| 181 | ## |
| 182 | ## Setup Cache-As-Ram |
| 183 | ## |
| 184 | mainboardinit cpu/amd/car/cache_as_ram.inc |
| 185 | end |
| 186 | |
| 187 | |
| 188 | ### |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 189 | ### This is the early phase of LinuxBIOS startup. |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 190 | ### Things are delicate and we test to see if we should |
| 191 | ### failover to another image. |
| 192 | ### |
| 193 | if HAVE_FAILOVER_BOOT |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 194 | if USE_FAILOVER_IMAGE |
| 195 | if USE_DCACHE_RAM |
| 196 | ldscript /arch/i386/lib/failover_failover.lds |
| 197 | end |
| 198 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 199 | else |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 200 | if USE_FALLBACK_IMAGE |
| 201 | if USE_DCACHE_RAM |
| 202 | ldscript /arch/i386/lib/failover.lds |
| 203 | end |
| 204 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 205 | end |
| 206 | |
| 207 | ### |
| 208 | ### O.k. We aren't just an intermediary anymore! |
| 209 | ### |
| 210 | |
| 211 | ## |
| 212 | ## Setup RAM |
| 213 | ## |
| 214 | if USE_DCACHE_RAM |
| 215 | if CONFIG_USE_INIT |
| 216 | initobject auto.o |
| 217 | else |
| 218 | mainboardinit ./auto.inc |
| 219 | end |
| 220 | end |
| 221 | |
| 222 | ## |
| 223 | ## Include the secondary configuration files |
| 224 | ## |
| 225 | if CONFIG_CHIP_NAME |
| 226 | config chip.h |
| 227 | end |
| 228 | |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 229 | chip northbridge/amd/amdk8/root_complex # Root complex |
| 230 | device apic_cluster 0 on # APIC cluster |
| 231 | chip cpu/amd/socket_939 # Socket 939 CPU |
| 232 | device apic 0 on end # APIC |
| 233 | end |
| 234 | end |
Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame] | 235 | |
Uwe Hermann | 322076c | 2007-09-24 20:00:32 +0000 | [diff] [blame^] | 236 | device pci_domain 0 on # PCI domain |
| 237 | chip northbridge/amd/amdk8 # mc0 |
| 238 | device pci 18.0 on # Northbridge |
| 239 | # Devices on link 0, link 0 == LDT 0 |
| 240 | chip southbridge/nvidia/ck804 # Southbridge |
| 241 | device pci 0.0 on end # HT |
| 242 | device pci 1.0 on # LPC |
| 243 | chip superio/ite/it8712f # Super I/O |
| 244 | device pnp 2e.0 off # Floppy |
| 245 | io 0x60 = 0x3f0 |
| 246 | irq 0x70 = 6 |
| 247 | drq 0x74 = 2 |
| 248 | end |
| 249 | device pnp 2e.1 on # Com1 |
| 250 | io 0x60 = 0x3f8 |
| 251 | irq 0x70 = 4 |
| 252 | end |
| 253 | device pnp 2e.2 off # Com2 |
| 254 | io 0x60 = 0x2f8 |
| 255 | irq 0x70 = 3 |
| 256 | end |
| 257 | device pnp 2e.3 on # Parallel port |
| 258 | io 0x60 = 0x378 |
| 259 | irq 0x70 = 7 |
| 260 | end |
| 261 | device pnp 2e.4 on # Environment controller |
| 262 | io 0x60 = 0x290 |
| 263 | io 0x62 = 0x0000 |
| 264 | irq 0x70 = 0x00 |
| 265 | end |
| 266 | device pnp 2e.5 on # PS/2 keyboard |
| 267 | io 0x60 = 0x60 |
| 268 | io 0x62 = 0x64 |
| 269 | irq 0x70 = 1 |
| 270 | irq 0x71 = 2 |
| 271 | end |
| 272 | device pnp 2e.6 on # PS/2 mouse |
| 273 | irq 0x70 = 12 |
| 274 | irq 0x71 = 2 |
| 275 | end |
| 276 | device pnp 2e.7 on # GPIO config |
| 277 | # Set GPIO 1 & 2 |
| 278 | io 0x25 = 0x0000 |
| 279 | # Set GPIO 3 & 4 |
| 280 | io 0x27 = 0x2540 |
| 281 | # GPIO Polarity for Set 3 |
| 282 | io 0xb2 = 0x2100 |
| 283 | # GPIO Pin Internal Pull up for Set 3 |
| 284 | io 0xba = 0x0100 |
| 285 | # Simple I/O register config |
| 286 | io 0xc0 = 0x0000 |
| 287 | io 0xc2 = 0x2540 |
| 288 | io 0xc8 = 0x0000 |
| 289 | io 0xca = 0x0500 |
| 290 | end |
| 291 | device pnp 2e.8 off end # Midi port |
| 292 | device pnp 2e.9 off end # Game port |
| 293 | device pnp 2e.a off end # IR |
| 294 | end |
| 295 | end |
| 296 | device pci 1.1 on # SM 0 |
| 297 | # chip drivers/generic/generic #dimm 0-0-0 |
| 298 | # device i2c 50 on end |
| 299 | # end |
| 300 | # chip drivers/generic/generic #dimm 0-0-1 |
| 301 | # device i2c 51 on end |
| 302 | # end |
| 303 | # chip drivers/generic/generic #dimm 0-1-0 |
| 304 | # device i2c 52 on end |
| 305 | # end |
| 306 | # chip drivers/generic/generic #dimm 0-1-1 |
| 307 | # device i2c 53 on end |
| 308 | # end |
| 309 | # chip drivers/generic/generic #dimm 1-0-0 |
| 310 | # device i2c 54 on end |
| 311 | # end |
| 312 | # chip drivers/generic/generic #dimm 1-0-1 |
| 313 | # device i2c 55 on end |
| 314 | # end |
| 315 | # chip drivers/generic/generic #dimm 1-1-0 |
| 316 | # device i2c 56 on end |
| 317 | # end |
| 318 | # chip drivers/generic/generic #dimm 1-1-1 |
| 319 | # device i2c 57 on end |
| 320 | # end |
| 321 | end |
| 322 | device pci 2.0 on end # USB 1.1 |
| 323 | device pci 2.1 on end # USB 2 |
| 324 | device pci 4.0 off end # Onboard audio (ACI) |
| 325 | device pci 4.1 off end # Onboard modem (MCI) |
| 326 | device pci 6.0 on end # IDE |
| 327 | device pci 7.0 on end # SATA 1 |
| 328 | device pci 8.0 on end # SATA 0 |
| 329 | device pci 9.0 on end # PCI |
| 330 | device pci a.0 on end # NIC |
| 331 | device pci b.0 on end # PCI E 3 |
| 332 | device pci c.0 on end # PCI E 2 |
| 333 | device pci d.0 on end # PCI E 1 |
| 334 | device pci e.0 on end # PCI E 0 |
| 335 | register "ide0_enable" = "1" |
| 336 | register "ide1_enable" = "1" |
| 337 | register "sata0_enable" = "1" |
| 338 | register "sata1_enable" = "1" |
| 339 | # register "mac_eeprom_smbus" = "3" |
| 340 | # register "mac_eeprom_addr" = "0x51" |
| 341 | end |
| 342 | end |
| 343 | device pci 18.1 on end |
| 344 | device pci 18.2 on end |
| 345 | device pci 18.3 on end |
| 346 | end |
| 347 | end |
| 348 | end |