Patrick Georgi | ea063cb | 2020-05-08 19:28:13 +0200 | [diff] [blame] | 1 | /* inteltool - dump all registers on an Intel CPU + chipset based system */ |
Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Michael Niewöhner | 9952e72 | 2020-03-13 22:22:26 +0100 | [diff] [blame] | 3 | |
| 4 | #include <stdio.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <inttypes.h> |
| 7 | #include <commonlib/helpers.h> |
| 8 | #include "inteltool.h" |
| 9 | |
| 10 | #define SUNRISE_LPC_BC 0xdc |
| 11 | |
| 12 | static const io_register_t sunrise_lpc_cfg_registers[] = { |
| 13 | {0x00, 4, "ID"}, |
| 14 | {0x04, 2, "CMD"}, |
| 15 | {0x06, 2, "STS"}, |
| 16 | {0x08, 1, "RID"}, |
| 17 | {0x09, 1, "CC[3]"}, |
| 18 | {0x0A, 1, "CC[2]"}, |
| 19 | {0x0B, 1, "CC[1]"}, |
| 20 | {0x0C, 1, "CC[0]"}, |
| 21 | {0x0E, 1, "HTYPE"}, |
| 22 | {0x2C, 4, "SS"}, |
| 23 | {0x34, 1, "CAPP"}, |
| 24 | {0x64, 1, "SCNT"}, |
| 25 | {0x80, 2, "IOD"}, |
| 26 | {0x82, 2, "IOE"}, |
| 27 | {0x84, 4, "LGIR1"}, |
| 28 | {0x88, 4, "LGIR2"}, |
| 29 | {0x8C, 4, "LGIR3"}, |
| 30 | {0x90, 4, "LGIR4"}, |
| 31 | {0x94, 4, "ULKMC"}, |
| 32 | {0x98, 4, "LGMR"}, |
| 33 | {0xD0, 2, "FS1"}, |
| 34 | {0xD4, 2, "FS2"}, |
| 35 | {0xD8, 2, "BDE"}, |
| 36 | {0xDC, 1, "BC"}, |
| 37 | {0xE0, 4, "PCCTL"}, |
| 38 | }; |
| 39 | |
| 40 | static const io_register_t sunrise_espi_cfg_registers[] = { |
| 41 | {0x00, 4, "ESPI_DID_VID"}, |
| 42 | {0x04, 4, "ESPI_STS_CMD"}, |
| 43 | {0x08, 4, "ESPI_CC_RID"}, |
| 44 | {0x0C, 4, "ESPI_BIST_HTYPE_PLT_CLS"}, |
| 45 | {0x2C, 4, "ESPI_SS"}, |
| 46 | {0x34, 4, "ESPI_CAPP"}, |
| 47 | {0x80, 4, "ESPI_IOD_IOE"}, |
| 48 | {0x84, 4, "ESPI_LGIR1"}, |
| 49 | {0x88, 4, "ESPI_LGIR2"}, |
| 50 | {0x8C, 4, "ESPI_LGIR3"}, |
| 51 | {0x90, 4, "ESPI_LGIR4"}, |
| 52 | {0x94, 4, "ESPI_ULKMC"}, |
| 53 | {0x98, 4, "ESPI_LGMR"}, |
| 54 | {0xD0, 4, "ESPI_FS1"}, |
| 55 | {0xD4, 4, "ESPI_FS2"}, |
| 56 | {0xD8, 4, "ESPI_BDE"}, |
| 57 | {0xDC, 4, "ESPI_BC"}, |
| 58 | }; |
| 59 | |
Brandon Weeks | 7ee7b13 | 2023-12-26 15:55:03 -0800 | [diff] [blame] | 60 | static const io_register_t alderlake_espi_cfg_registers[] = { |
| 61 | {0x00, 4, "ESPI_DID_VID"}, |
| 62 | {0x04, 4, "ESPI_STS_CMD"}, |
| 63 | {0x08, 4, "ESPI_CC_RID"}, |
| 64 | {0x2C, 4, "ESPI_SS"}, |
| 65 | {0x34, 4, "ESPI_CAPP"}, |
| 66 | {0x80, 4, "ESPI_IOD_IOE"}, |
| 67 | {0x84, 4, "ESPI_LGIR1"}, |
| 68 | {0x88, 4, "ESPI_LGIR2"}, |
| 69 | {0x8C, 4, "ESPI_LGIR3"}, |
| 70 | {0x90, 4, "ESPI_LGIR4"}, |
| 71 | {0x94, 4, "ESPI_ULKMC"}, |
| 72 | {0x98, 4, "ESPI_LGMR"}, |
| 73 | {0xA0, 4, "ESPI_CS1IORE"}, |
| 74 | {0xA4, 4, "ESPI_CS1GIR1"}, |
| 75 | {0xA8, 4, "ESPI_CS1GMR1"}, |
| 76 | {0xD8, 4, "ESPI_BDE"}, |
| 77 | {0xDC, 4, "ESPI_BC"}, |
| 78 | }; |
| 79 | |
Michael Niewöhner | 9952e72 | 2020-03-13 22:22:26 +0100 | [diff] [blame] | 80 | int print_lpc(struct pci_dev *sb, struct pci_access *pacc) |
| 81 | { |
| 82 | size_t i, cfg_registers_size = 0; |
| 83 | const io_register_t *cfg_registers; |
| 84 | struct pci_dev *dev = NULL; |
| 85 | uint32_t bc; |
| 86 | |
| 87 | printf("\n========== LPC/eSPI =========\n\n"); |
| 88 | |
| 89 | switch (sb->device_id) { |
| 90 | case PCI_DEVICE_ID_INTEL_H110: |
| 91 | case PCI_DEVICE_ID_INTEL_H170: |
| 92 | case PCI_DEVICE_ID_INTEL_Z170: |
| 93 | case PCI_DEVICE_ID_INTEL_Q170: |
| 94 | case PCI_DEVICE_ID_INTEL_Q150: |
| 95 | case PCI_DEVICE_ID_INTEL_B150: |
| 96 | case PCI_DEVICE_ID_INTEL_C236: |
| 97 | case PCI_DEVICE_ID_INTEL_C232: |
| 98 | case PCI_DEVICE_ID_INTEL_QM170: |
| 99 | case PCI_DEVICE_ID_INTEL_HM170: |
| 100 | case PCI_DEVICE_ID_INTEL_CM236: |
| 101 | case PCI_DEVICE_ID_INTEL_HM175: |
| 102 | case PCI_DEVICE_ID_INTEL_QM175: |
| 103 | case PCI_DEVICE_ID_INTEL_CM238: |
| 104 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: |
| 105 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: |
| 106 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: |
| 107 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: |
| 108 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: |
| 109 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: |
| 110 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: |
| 111 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: |
| 112 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: |
| 113 | case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: |
| 114 | dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); |
| 115 | if (!dev) { |
| 116 | printf("LPC/eSPI interface not found.\n"); |
| 117 | return 1; |
| 118 | } |
| 119 | bc = pci_read_long(dev, SUNRISE_LPC_BC); |
| 120 | if (bc & (1 << 2)) { |
| 121 | printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); |
| 122 | cfg_registers = sunrise_espi_cfg_registers; |
| 123 | cfg_registers_size = ARRAY_SIZE(sunrise_espi_cfg_registers); |
| 124 | |
| 125 | } else { |
| 126 | printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n"); |
| 127 | cfg_registers = sunrise_lpc_cfg_registers; |
| 128 | cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); |
| 129 | } |
| 130 | break; |
Brandon Weeks | 7ee7b13 | 2023-12-26 15:55:03 -0800 | [diff] [blame] | 131 | case PCI_DEVICE_ID_INTEL_ADL_N: |
| 132 | dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); |
| 133 | if (!dev) { |
| 134 | printf("LPC/eSPI interface not found.\n"); |
| 135 | return 1; |
| 136 | } |
| 137 | printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); |
| 138 | cfg_registers = alderlake_espi_cfg_registers; |
| 139 | cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers); |
| 140 | break; |
Michael Niewöhner | 9952e72 | 2020-03-13 22:22:26 +0100 | [diff] [blame] | 141 | default: |
| 142 | printf("Error: Dumping LPC/eSPI on this southbridge is not (yet) supported.\n"); |
| 143 | return 1; |
| 144 | } |
| 145 | |
| 146 | for (i = 0; i < cfg_registers_size; i++) { |
| 147 | switch (cfg_registers[i].size) { |
| 148 | case 4: |
| 149 | printf("0x%04x: 0x%08x (%s)\n", |
| 150 | cfg_registers[i].addr, |
| 151 | pci_read_long(dev, cfg_registers[i].addr), |
| 152 | cfg_registers[i].name); |
| 153 | break; |
| 154 | case 2: |
| 155 | printf("0x%04x: 0x%04x (%s)\n", |
| 156 | cfg_registers[i].addr, |
| 157 | pci_read_word(dev, cfg_registers[i].addr), |
| 158 | cfg_registers[i].name); |
| 159 | break; |
| 160 | case 1: |
| 161 | printf("0x%04x: 0x%02x (%s)\n", |
| 162 | cfg_registers[i].addr, |
| 163 | pci_read_byte(dev, cfg_registers[i].addr), |
| 164 | cfg_registers[i].name); |
| 165 | break; |
| 166 | default: |
| 167 | printf("Error: register size %d not implemented.\n", |
| 168 | cfg_registers[i].size); |
| 169 | break; |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | if (dev) |
| 174 | pci_free_dev(dev); |
| 175 | |
| 176 | return 0; |
| 177 | } |