Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip northbridge/intel/sandybridge |
| 4 | device domain 0 on |
| 5 | subsystemid 0x1043 0x84ca inherit |
| 6 | chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH |
| 7 | register "gen1_dec" = "0x000c0291" |
| 8 | |
| 9 | device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) |
| 10 | device pci 1c.1 off end # PCIe Port #2 |
| 11 | device pci 1c.2 off end # PCIe Port #3 |
| 12 | device pci 1c.3 off end # PCIe Port #4 |
| 13 | device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot) |
| 14 | device pci 1c.5 on end # PCIe Port #6 |
| 15 | device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083) |
| 16 | device pci 1c.7 off end # PCIe Port #8 |
| 17 | device pci 1f.0 on # LPC bridge |
| 18 | chip superio/nuvoton/nct6779d |
| 19 | device pnp 2e.1 off end # Parallel |
| 20 | device pnp 2e.2 on # UART A |
| 21 | io 0x60 = 0x3f8 # COM1 address |
| 22 | irq 0x70 = 4 |
| 23 | # Below are global config settings to replicate OEM |
| 24 | drq 0x26 = 0x10 # Before accessing CR10/11/13/14, CR26:4 must be set to 1 |
| 25 | drq 0x13 = 0xff # IRQs 0-15 active low |
| 26 | drq 0x14 = 0xff |
| 27 | drq 0x1a = 0x02 |
| 28 | drq 0x1b = 0x60 |
| 29 | drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI |
| 30 | end |
| 31 | device pnp 2e.3 off end # UART B, IR |
| 32 | device pnp 2e.5 on # PS2 KBC |
| 33 | io 0x60 = 0x0060 # KBC1 base |
| 34 | io 0x62 = 0x0064 # KBC2 base |
| 35 | irq 0x70 = 1 # Keyboard IRQ |
| 36 | irq 0x72 = 12 # Mouse IRQ |
| 37 | drq 0xf0 = 0x82 # KBC 12Mhz/A20 speed/sw KBRST |
| 38 | drq 0x2a = 0x48 # UART A, PS/2 mouse, PS/2 keyboard |
| 39 | drq 0x22 = 0xd7 # Power down UART B and LPT |
| 40 | end |
| 41 | device pnp 2e.6 off end # CIR |
| 42 | device pnp 2e.8 on # WDT1 |
| 43 | drq 0xe0 = 0x7f # GP07 output |
| 44 | drq 0xe1 = 0x80 # GP07 high |
| 45 | end |
| 46 | device pnp 2e.a on # ACPI |
| 47 | drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility |
| 48 | drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME |
| 49 | end |
| 50 | device pnp 2e.b on # HWM, front panel LED |
| 51 | io 0x60 = 0x290 # HWM address |
| 52 | io 0x62 = 0 # SB-TSI address (not used) |
| 53 | drq 0xe4 = 0xf9 # GP50, GP52, PWROK# |
| 54 | drq 0xf0 = 0x3e # Enable all fan input debouncers |
| 55 | end |
| 56 | device pnp 2e.e off end # CIR wake-up |
| 57 | device pnp 2e.f on # GPIO PP/OD select |
| 58 | drq 0xe4 = 0xfc # GP50,GP51 PP |
| 59 | drq 0xe6 = 0x7f # GP7x OD |
| 60 | end |
| 61 | device pnp 2e.9 off end # GPIO 8 |
| 62 | device pnp 2e.308 on end # GPIO by I/O |
| 63 | device pnp 2e.108 on end # GPIO 0 |
| 64 | device pnp 2e.109 on end # GPIO 1 |
| 65 | device pnp 2e.209 on # GPIO 2 |
| 66 | drq 0xe0 = 0xbf # GP26 output |
| 67 | drq 0xe1 = 0xc0 # GP26 high |
| 68 | end |
| 69 | device pnp 2e.309 off end # GPIO 3 |
| 70 | device pnp 2e.409 off end # GPIO 4 |
| 71 | device pnp 2e.509 on # GPIO 5 |
| 72 | drq 0xf4 = 0xfc # GP50,GP51 output |
| 73 | drq 0xf5 = 0xc4 # GP50,GP51 low |
| 74 | end |
| 75 | device pnp 2e.609 off end # GPIO 6 |
| 76 | device pnp 2e.709 off end # GPIO 7 |
| 77 | end |
Fabian Groffen | 316e2f4 | 2023-05-10 21:32:47 +0200 | [diff] [blame^] | 78 | chip drivers/pc80/tpm |
| 79 | device pnp 4e.0 on end # TPM |
| 80 | end |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 81 | end |
| 82 | end |
| 83 | end |
| 84 | end |