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review.coreboot.org / coreboot / 31402178c56108e752b95c34562b6e3554a2c1d8 / . / src / southbridge / intel / common / rtc.c
blob: 933ac6349ff1e0a016187513a30ce93b931893d7 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]2
Angel Pons4dc85f12021-02-08 00:24:32 +0100[diff] [blame]3#define __SIMPLE_DEVICE__
4
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]5#include <console/console.h>
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]6#include <device/pci_ops.h>
Elyes Haouasddd43de2022-10-02 20:02:23 +0200[diff] [blame]7#include <device/pci_type.h>
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]8#include <elog.h>
Elyes Haouasddd43de2022-10-02 20:02:23 +0200[diff] [blame]9#include <pc80/mc146818rtc.h>
10#include <security/vboot/vbnv.h>
11
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]12#include "pmutil.h"
13#include "rtc.h"
14
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]15#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]16
17int rtc_failure(void)
18{
Angel Pons4dc85f12021-02-08 00:24:32 +0100[diff] [blame]19 return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) & RTC_BATTERY_DEAD);
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]20}
21
22void sb_rtc_init(void)
23{
24 int rtc_failed = rtc_failure();
25
26 if (rtc_failed) {
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]27 if (CONFIG(ELOG))
Patrick Rudolph6b931122018-11-01 17:48:37 +0100[diff] [blame]28 elog_add_event(ELOG_TYPE_RTC_RESET);
29 pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
30 ~RTC_BATTERY_DEAD, 0);
31 }
32
33 printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed);
34
35 cmos_init(rtc_failed);
36}
37
38int vbnv_cmos_failed(void)
39{
40 return rtc_failure();
41}