| Angel Pons | 20a609f | 2021-02-06 23:22:33 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
| 5 | #include <device/pci_ops.h> |
| 6 | #include <types.h> |
| 7 | |
| 8 | #include "me.h" |
| 9 | |
| 10 | #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 11 | |
| 12 | #define ETR3 0xac |
| 13 | #define ETR3_CWORWRE (1 << 18) |
| 14 | #define ETR3_CF9GR (1 << 20) |
| 15 | #define ETR3_CF9LOCK (1 << 31) |
| 16 | |
| 17 | void set_global_reset(const bool enable) |
| 18 | { |
| 19 | u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); |
| 20 | |
| 21 | /* Clear CF9 Without Resume Well Reset Enable */ |
| 22 | etr3 &= ~ETR3_CWORWRE; |
| 23 | |
| 24 | /* CF9GR indicates a Global Reset */ |
| 25 | if (enable) |
| 26 | etr3 |= ETR3_CF9GR; |
| 27 | else |
| 28 | etr3 &= ~ETR3_CF9GR; |
| 29 | |
| 30 | pci_write_config32(PCH_LPC_DEV, ETR3, etr3); |
| 31 | } |