| Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/asm.h> |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 4 | #include <cpu/cortex_a57.h> |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 5 | |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 6 | /* |
| 7 | * It is observed that BTB contains stale data after power on reset. This could |
| 8 | * lead to unexpected branching and crashes at random intervals during the boot |
| 9 | * flow. Thus, invalidate the BTB immediately after power on reset. |
| 10 | */ |
| 11 | .macro t210_a57_fixup |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 12 | /* |
| 13 | * Invalidate BTB along with I$ to remove any stale entries |
| 14 | * from the branch predictor array. |
| 15 | */ |
| 16 | mrs x0, CPUACTLR_EL1 |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 17 | orr x0, x0, #BTB_INVALIDATE |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 18 | msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ |
| 19 | dsb sy |
| 20 | isb |
| 21 | ic iallu /* invalidate */ |
| 22 | dsb sy |
| 23 | isb |
| 24 | |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 25 | bic x0, x0, #BTB_INVALIDATE |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 26 | msr CPUACTLR_EL1, x0 /* restore original CPUACTLR_EL1 */ |
| 27 | dsb sy |
| 28 | isb |
| 29 | |
| 30 | .rept 7 |
| 31 | nop /* wait */ |
| 32 | .endr |
| 33 | |
| 34 | /* |
| 35 | * Extract OSLK bit and check if it is '1'. This bit remains '0' |
| 36 | * for A53. If '1', turn off regional clock gating and request |
| 37 | * warm reset. |
| 38 | */ |
| 39 | mrs x0, oslsr_el1 |
| 40 | and x0, x0, #2 /* extract oslk bit */ |
| 41 | mrs x1, mpidr_el1 |
| 42 | bics xzr, x0, x1, lsr #7 /* 0 if slow cluster */ |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 43 | b.eq 1000f |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 44 | mov x0, xzr |
| 45 | msr oslar_el1, x0 /* os lock stays 0 across warm reset */ |
| 46 | mov x3, #3 |
| 47 | movz x4, #0x8000, lsl #48 |
| 48 | msr CPUACTLR_EL1, x4 /* turn off RCG */ |
| 49 | isb |
| 50 | msr rmr_el3, x3 /* request warm reset */ |
| 51 | isb |
| 52 | dsb sy |
| 53 | wfi |
| 54 | |
| 55 | /* |
| 56 | * These nops are here so that speculative execution won't harm us |
| 57 | * before we are done warm reset. |
| 58 | */ |
| 59 | .rept 65 |
| 60 | nop |
| 61 | .endr |
| 62 | |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 63 | 1000: |
| 64 | /* Restore os lock */ |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 65 | mov x0, #1 |
| 66 | msr oslar_el1, x0 |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 67 | .endm |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 68 | |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 69 | ENTRY(stage_entry) |
| 70 | t210_a57_fixup |
| Furquan Shaikh | 25fbe2a | 2015-07-10 15:29:13 -0700 | [diff] [blame] | 71 | |
| Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 72 | /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ |
| 73 | bl arm64_init_cpu |
| 74 | |
| 75 | /* Jump to Tegra-specific C entry point. */ |
| 76 | bl ramstage_entry |
| 77 | ENDPROC(stage_entry) |